I'm pretty familair with the standard 2-DFF schemes for synchronization.
I came across the URL below and have a question about Figure 1b:
Why not use the clock-enable on the FF on the right-hand side instead of having the flop re-latch data at every clock? Is this because a CE on a flip-flop in an ASIC may not be available, as it is on an FPGA?
Thanks. H.