I'm pretty familair with the standard 2-DFF schemes for synchronization.
I came across the URL below and have a question about Figure 1b:
Why not use the clock-enable on the FF on the right-hand side instead of having the flop re-latch data at every clock? Is this because a CE on a flip-flop in an ASIC may not be available, as it is on an FPGA?
Thanks. H.
It is the same. Maybe it is just for illustration purpose.
Regards, Thomas
More precisely: CE in (Xilinx) FPGAs is always implemented by recirculating data back from Q to D. Not really any clock gating, for reasons that have been amply explained in this ng. Peter Alfke
Just to be clear, the flip-flops inside the Xilinx parts use the same MUX structure to feed data back, and the CE really toggles the SEL line on the MUX?
Thanks. HW.
You got it ! Peter
You got it ! Peter
Hi Peter,
Does it use a dedicated feedback line or local routing?
Best regards,
Ben
Dedicated feedback, of course. It has to be blinding fast, so that the set-up time of CE is kept low. There really is no choice, since gating the clock with a potentially asynchronous input would be a disaster. Peter Alfke, Xilinx Applications (hoping to make this a single posting...)
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