Multiple Virtex 2 Pro's, DCM and CLKIN_DIVIDE_BY_2

Howdy John,

I know that the phase is not deterministic for the CLKDV output, and I'd strongly suspect the same for the input divider.

The only (not so good) way to get what you want is to have some monitoring logic which resets the DCM until it has the correct phase - which of course, means it needs to somehow have visability into what the correct phase is supposed to be.

I believe the only straight forward way of doing what you want is to do the divide before the fanout. The next, not nearly so good way, is to drive the global clocks of all the devices with the 2x clock, but use a board wide clock enable on all your logic. Just thinking out loud here. Hmmm... anyone ever used a BUFG enable/mux as a clock enable?

Good luck,

Marc

Marc -

Thanks for your thoughts, I hope the Xilinx folks can add some more insight on the topic.

John P

I hate to say this, but you are trying to do the impossible. If you feed a common reference frequency to several chips, and locally divide or multiply the frequency by the same number in each chip, there is NO WAY to automatically assure synchronism between the chips. Your only solution is a separate communication link between the chips that enforces synchronism. (Once successful, the link becomes redundant, but it will be difficult to take advantage of that.) Far-out scheme: You could skip one period of the common clock, and locally detect that missing pulse as a synchronizing mark. But don't try that with DCMs... Peter Alfke, Xilinx Applications

Sorry, I got carried away: When you multiply the frequency locally, the chips are of course in step, and if you need to refer to the lower frequency, you have it at the input. No problem.

The unsolvable problem occurs only when you do a local divide. Then the result is ambiguous between the chips, and there is no way to resolve that.. I hope I caught this mistake in time Peter Alfke, Xilinx Applications

Peter -

Thanks for the feedback. As I noted in my original posting, I can cleanly stop the input clock to the DCM, assert the DCM reset, then cleanly re-enable the clock. Since I am using the CLKIN_DIVIDE_BY_2 mode, my question is if that "input" divider on the DCM gets reset by the DCM RST pin or not. If it is reset by the RST pin, then all the DCMs in my system should be able to be "in-sync".

Thanks for being a great resource in this forum!

John Providenza

John, I still do not think that this would work. And if it did, it would still be a precarious thing, with no re-enforcement. Bite the bullet, and strap an extra connection between the chips... Peter Alfke

Howdy John,

Looking back over your posting(s), you don't explictly say that the clock inside of the FPGA has to be phase aligned with the clock outside. If that's the case, you don't need the DCM:

You could probably use your reset to control how a logic based FF initializes. The FF and the routing to and from it could be locked down so it doesn't vary between all the FPGA's.

If you do need the internal clock to be phase aligned with the external, you could route the output of the FF divider to a DCM which has a phase offset dialed in (that you'll have to come up with manually). Not optimal, but with correct attention to timing constraints, I think it could work.

Marc