Will this DCM cascade track a frequency offset clock?

Hi all,

I need to generate a 20MHz clock from a 10MHz clock on a V2Pro.

Plan is to use 2 DCMs:

1st DCM: 10MHz into CLKIN Use CLKFX output with default of M = 4 and D = 1 to get 40MHz. I need to leave CLKFB unconnected because CLK0 and CLK2X will be below 24MHz. Also, since I am using CLKFX, I can leave CLKFB open since it is ok for CLKFX clock to be out of phase with the input 10MHz clock.

2nd DCM:

40MHz into CLKIN 20MHz out of CLKDV CLKFB gets CLK0.

First question - will that work?

Next question:

The input 10MHz clock can be varied by +/- 25 parts per million to give a frequency offset.

So, input period is (1/10e6) +/- 2.5ps.

The +/-2.5 ps seems to be way less than the cycle and period jitter spec of the DCM so I am not worried about that.

The input clock will be held at each offset for 20ms minimum. Also, there is 800us available for the DCMs to adjust to the new input frequency.

I see that the lock time of the DCM is 10ms and I assume this is just at configuration time?

So, am i right in thinking that my DCM cascade will track my freq offset when it is applied? Is there a spec somewhere that states how long it will take to adjust to the new input freq or is it instantaneous since the variance is only +/- 2.5ps?

Thanks for your time guys,

Ken

Reply to
Ken
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hi Ken,

First question - no. tried almost the same thing on Virtex 2 (was locking and losing lock periodically). What you should do is to multiply by a larger number using CLKFX as now, and then used FFs to divide the clock down for feeding it to the next DCM stage. In this fashion, the output jitter on DCM1/CLK0 is divided as well to be suitable for the DCM2/CLKIN jitter tolerance. I tried, it works PERFECTO! What happens, is that DCM multiplies whatever jitter you have at your clock source plus adding some cycle-cycle jitter, due to its tapped delay line nature. I think there is some web page in Xilinx website or tools that calculates that output jitter per given input jitter.

Regarding you 2nd question... I never saw anything specifiying the lock time in this case, however, i have noticed that the resets of DCMs cascaded in this way are to be held for much more than just 3/4/5 CLKIN cycles; exactly how much time, i cannot tell. but 20 ms is definitely sufficient.

Hope this helps.

Vladislav

Reply to
Vladislav Muravin

How, pray tell, do the FFs divide the jitter? The peak-to-peak jitter, measured in units of time, can only get worse though a FF divsion.

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How does the DCM multiply input jitter? Are you getting confused between pk-pk jitter in terms of time as opposed to pk-pk jitter in terms of unit intervals? If you look at the DCM input timing specs, you'll see they're specified in terms of time, not UIs. In my experience, problems with DCMs often derive from noise on the supplies from inadequate Vccaux bypassing. Whatever, I'll wait for Austin to post and clear this up! Cheers, Syms.

Reply to
Symon

Me too!

Reply to
Ken

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