Field-Programmable Gate Arrays

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Worth reading in Field-Programmable Gate Arrays

Bresenham Algorithms

Are there any Bresenham line drawing algorithms that are suitable for FPGA pipeline video streaming? In VHDL? b r a d @...
7 comments posted 21yrs
posted by bradsmallridge
7 comments posted 21yrs posted by bradsmallridge

Programmer + Cable

Hi, we want to reprogram Spartan FPGAs via JTAG. We are not using Xilinx development tools so which programmer + cable d...
1 comments posted 21yrs
posted by ALuPin
1 comments posted 21yrs posted by ALuPin

cannot get compedklib tool to work

Hello, I have a problem simulating a design made in Xilinx Platform Studio with EDK 6.3. The thing is, I cannot get com...
2 comments posted 21yrs
posted by zoinks
2 comments posted 21yrs posted by zoinks

ethernet

Hi all, I want to implement ethernet but I have no exprience about ethernet. Can you please recommend some thing. I can...
10 comments posted 21yrs
posted by usrdr
10 comments posted 21yrs posted by usrdr

Xilinx Answer Record 21127

Hi has anyone succeeded to find Answer Record 21127 on Xilinx website? there are lots of references to it, but the Answe...
7 comments posted 21yrs
posted by antti
7 comments posted 21yrs posted by antti

using a SDRAM FIFO

Hi there, I'm working on a packet analyzer on a Virtex2Pro xc2vp7 FPGA using Microblaze soft-core. My intention is to s...
3 comments posted 21yrs
posted by adrian.mora
3 comments posted 21yrs posted by adrian.mora

Xilinx Virtex 4 Configuration Frames

Hello All, I am looking at the reconfiguration capabilities of Virtex 4 devices. I have following questions related to...
0 comments posted 21yrs
posted by lovesinghal
0 comments posted 21yrs posted by lovesinghal

QUARTUS on Linux.

Hello: does anyone have a positive experience with Quartus /Linux using a JTAG interface ? Does it work well? What is th...
2 comments posted 21yrs
posted by ano
2 comments posted 21yrs posted by ano

Mapping problem due to invalid pins in UCF file

Hi.. I am currently working with Xilinx ISE 6.3i ..The design is in VHDL..I tried adding some extra inputs and outputs...
10 comments posted 21yrs
posted by gmethi
10 comments posted 21yrs posted by gmethi

System Reset / GSR with Virtex 2 & Virtex 4

Howdy Gang ! It seems we have some sort of a problem with system reset in one of our SoC. It appears that after the boa...
4 comments posted 21yrs
posted by russelmann
4 comments posted 21yrs posted by russelmann

more and more and more issues with Xilinx tools

Hi all, FPGA are fun to work with ... when the tools work. New versions of the tools come out, then serice packs, but t...
11 comments posted 21yrs
posted by antti
11 comments posted 21yrs posted by antti

Nondeterministic ISE Placement

I remember a few years ago we would have to run ISE PAR several times in order to meet timing. One we had a decent layo...
1 comments posted 21yrs
posted by tomahawkins
1 comments posted 21yrs posted by tomahawkins