Hi there,
I'm working on a packet analyzer on a Virtex2Pro xc2vp7 FPGA using Microblaze soft-core. My intention is to save packets recieved from the network in SDRAM for later process. I have been thinking of using a SDRAM FIFO to be able to process the packets after been saved in memory. As I am working with EDK 6.3 I was thinking of using a FIFO IP core to be used in SDRAM. Can this be done this way? EDK doesn't include any FIFO IP core on the predesigned cores. I also have thought of creating a FIFO with Xilinx COREGEN and then including the FIFO in my EDK project but I can'f figure the way of exporting the .vhd files created by COREGEN into my EDK project. Has anyone ever used a FIFO in external memory with positive results? Which is the best way to do this? Any advice will be appreciated since I am quite a newbie with FPGA's.
Thanks in advance.
Adrian Mora.