how to apply different stimulus files to a test bench

I am new to varification field. i have just written small test benches but for the first time i have to write a big. The equirement is like this.

The main test bench should run from ModelSim. The selection of the UUT will be through VHDL. Once invoked, the code will pause and query the user for the stimulus file name and output file name.

Compare the generated and the expected results and should disply the warnings and error. Also should generate a output file for this.

Can anyone guide me.

Thanking you.

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techie
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The best book I've read on the subject is "Writing Testbenches: Functional Verification of HDL Models" by Janick Bergeron.

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Bob Perlman Cambrian Design Works

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Bob Perlman

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