System Reset / GSR with Virtex 2 & Virtex 4

First, the registers are not always cleared on power up. When asynchronous set/reset logic isn't used, synthesizers often bundle other logic into the synchronous set/reset pins of the flops beyond system set/reset. The FDS and FDSE primitives (anything with a set but not reset) power up to logic 1 unless the user overrides the value with an INIT=R attribute. The FD, FDR, FDRE, FDRS, FDRSE primitives (anything with a reset) power up to logic 0 unless the user overrides the value with an INIT=S attribute. I haven't included the register primitives with async set/reset in the lists but the idea carries through. Some synthesizers also support register initialization in the code, producing the INIT=S and INIT=R attributes from the initializations.

To get a synchronous reset into the design without pressing a reset *I* would just use a countdown that starts at power up and keeps the system in reset (except for the counter) until the count expires. I don't want to get in the business of async resets without additional controls to guarantee the deassertion of reset is synchronous where needed.

Just to confirm and expand on John_H's posting: At the end of configuration, Xilinx applies an asynchronous (p)reset to all flip-flops. That's the good news. The bad news is that the trailing edge of this initialization signal, even when it has been synchronized to the clock, has such a long propagation delay, that it often straddles several incoming clock periods. As a result, state machines can get half initiated and half running. The user is advised to augment the "free" initialization with deliberate synchronous initialization of critical flip-flops. Peter Alfke, Xilinx Applications.

Thanks for the feed back John and Peter.

Quick follow up question:

I have a reset block which prolongs the reset and does a few other things. In addition to the Reset Button, I also take the lock output from the DPLL that generates the clock to the SoC. As long as there is no lock, I hold the system in reset, and even after a lock for some more cycles. So perhaps my reset should not be a problem after all ? If I assume that the lock signal of a DPLL would be asserted some time AFTER configuration ?!

Best Regards, rudi ============================================================= Rudolf Usselmann, ASICS World Services,

As long as your reset is synchronous, you have a solid solution.

Keep in mind there's a programming option to hold of operation of the FPGA until the DLLs are stable. If you *don't* engage this option, your reset ciruit should take care of everything for you.