Field-Programmable Gate Arrays

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CPLD Fitting problem

Hello eveyone, I have a design involving a Lattice ispMACH4384. The pinout is already fixed. I have to make a 5:1 24bit...
3 comments posted 21yrs
posted by Falk.Brunner
3 comments posted 21yrs posted by Falk.Brunner

RISCWatch and JTAG

Hello! Is there any hardware documentation to RISCWatch of PPC405 in Xilinx devices? I look for waveforms describe the...
1 comments posted 21yrs
posted by krzysiek
1 comments posted 21yrs posted by krzysiek

using less brams for powerpc code

Hi, I have made a simple design for a powerpc. The code is running from bram and starts at 0xFFFF_0000, because I am us...
0 comments posted 21yrs
posted by someone
0 comments posted 21yrs posted by someone

FSM stops working

Hi all I've been working on a project that has uses a FSM and have run out o ideas about why it's not working. There ar...
7 comments posted 21yrs
posted by jralston
7 comments posted 21yrs posted by jralston

Virtex4 Block Ram : ISE6.3 Problem

We have just bought a new Virtex4 based devleopment board, but were having alot of trouble with the on-chip block RAM....
2 comments posted 21yrs
posted by luke.darnell
2 comments posted 21yrs posted by luke.darnell

spartan 3 designing board

Hiya, Ive lurked here for a while and have read the many arguments for and against designing a board or purchasing a de...
2 comments posted 21yrs
posted by googlinggoogler
2 comments posted 21yrs posted by googlinggoogler

GHDL under x86_64 Linux

Hi, Has anyone had success with running GHDL under an x86_64 distro? I use Suse 9.3 and I dont have the option of compi...
2 comments posted 21yrs
posted by send_no_spam_to_jimgeorge
2 comments posted 21yrs posted by send_no_spam_to_jimgeorge

Looking for core that does a vector product

Hi , I'm looking for a core in VHDL that does a vector product. Basically the following calculation: Out = Coeff(1) * I...
4 comments posted 21yrs
posted by andrewl
4 comments posted 21yrs posted by andrewl

Custom IP and BFM simulation help

I created some IP with the EDK wizard. It is only a 64-bit register--trying to understand how BFM simulation works befo...
1 comments posted 21yrs
posted by joeylrios
1 comments posted 21yrs posted by joeylrios

student round table

Sehr geehrte Frau Uschi Ronfeldt, ich werde an dem Treffen teilnehmen. Mit freundlichem Gruß, Benjamin Menküc
7 comments posted 21yrs
posted by benjamin
7 comments posted 21yrs posted by benjamin

How to make a 1.44MHz clock?

Hello, I have a spartan 3 starter board with 50MHz oscillator. I need to generate a 1.44MHz clock to drive an external...
10 comments posted 21yrs
posted by marcotoschi_no_spam
10 comments posted 21yrs posted by marcotoschi_no_spam

Reading the contents of a FPGA in-circuit.

Greetings. I saw only two posts in the archives about reading the contents of a FPGA. I have a design based around an A...
1 comments posted 21yrs
posted by sjhill
1 comments posted 21yrs posted by sjhill

VHDL vs. Schematic Capture

Hi Y'all : I have many years of experience with hardware design, software design & implementation etc (i.e. I'm comfort...
30 comments posted 21yrs
posted by xxx
30 comments posted 21yrs posted by xxx

How to download uClinux on Virtex4 Board.

Hi All, Have anybody tried downloading uClinux on Virtex4 board.We have got the bsp sources from http://www.itee.uq.edu...
4 comments posted 21yrs
posted by ivan.fed
4 comments posted 21yrs posted by ivan.fed

ALTERA EPXA1 SDRAM BUG

Hi all, have everyone experience about a second SDRAM with the Altera FPGA+HARCORE-CPU EPXA1? Its is unpossible for me...
0 comments posted 21yrs
posted by panse
0 comments posted 21yrs posted by panse