Latest threads in Field-Programmable Gate Arrays

What is a typical job scope when FPGAs are involved?

Hi all, I am looking at some FPGA related jobs and am finding that very few involve 100% FPGA design. Typically I am fi...

3 21yrs

no

3 21yrs no

Configuration-Frames for Virtex-II (Pro)

Hi, I try to find some information about the internal structure of the configuration-frames for Xilinx Virtex-II (Pro)...

1 21yrs

sven-habermann

1 21yrs sven-habermann

Accessing Bram

Which C function should I use to perform read or write into block ram (connected to opb bus with opb bus controller)? Xi...

5 21yrs

opb bram controller

In what way could I connect opb bram controller with a customized dual port ram? EDK does it automatically, but I'm not...

1 21yrs

Timing summary

Hi, I'm implementing a ddr-fifo buffer and when viewing the synthesis report on the ddr-fifo buffer by itself the timin...

3 21yrs

tebe7689

3 21yrs tebe7689

Problems with SDRAM and Altera Cyclone

I have a custom board with an altera EP1C12, a flash memory and a MT48LC4M32B2 SDRAM memory. Timings I set in SOPC buil...

5 21yrs

balulaz_at_libero_dot_it

5 21yrs balulaz_at_libero_dot_it

program simulation of the ML310 with XPS+ModelSim

Hi, thanks to the kind people on this group, I finally got a simulation of the ML310 board going. But I have another pr...

0 21yrs

zoinks

0 21yrs zoinks

Nios II - Booting software from Flash

Hi, Has anyone got NIOS software to boot from Flash? I'm working on a Stratix II-based design with onboard NIOS and per...

3 21yrs

totallytux

3 21yrs totallytux

Magical Mystery Tour of ISE environment variables

Hi *, I keep coming across answer records and script files containing the setting of undocumented environment variables...

7 21yrs

smd

7 21yrs smd

StateCAD 7.1i is broken?

Hi - Every once in a while, someone on this group asks about FSM design tools, and invariably StateCAD is mentioned. Xi...

1 21yrs

bobsrefusebin

1 21yrs bobsrefusebin

Xilinx CPLD fitter trouble, OK in Foundation4.1, bad in 6.3,7.1

IT took me quite a lot of time to realize that the newer webpack versions produces a fitter error without an error mess...

0 21yrs

techseller

0 21yrs techseller

Nios speed down

I've just moved from Quartus 4.0 to 5.0, re-generated a Nios design under SoPC Builder, and run the design through Quar...

1 21yrs

amyler

1 21yrs amyler

SPI slave select signals

Hi all, In an SPI interface i have got 4 slaves and one master What i wanted to know is wether the master can assert tw...

1 21yrs

praveen.kantharajapura

1 21yrs praveen.kantharajapura

Xilinx ISE 6.1i - Fatal Error

Haiii all,While I have updated my project directories from ISE webpack 5.1 to ISE 6.1i , the following error occurs dur...

1 21yrs

tvarvlsi

1 21yrs tvarvlsi

ISE 6.1 - Fatal Error

While I have updated my project directories from ISE webpack 5.1 to ISE 6.1i , the following error occurs during MAP &...

1 21yrs

anan_tv

1 21yrs anan_tv

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