Latest threads in Field-Programmable Gate Arrays

Xilinx Spartan 3 SSO Guidelines for 3.3V LVCMOS when using "series DCI"

Hi, I would like to use the Xilinx Spartan 3 DCI series source termination feature but the SSO guidelines from Pg25 of...

3 21yrs

andrew.newsgroup

3 21yrs andrew.newsgroup

Keypad controller implementation

Hi all, I want to implement a 6x6 keypad decoder in FPGA,i have got a reference design for that, but the limitation wit...

0 21yrs

praveen.kantharajapura

0 21yrs praveen.kantharajapura

[NEWBIE] Linux WebPack questions...

Greetings. I did take time to search the archives, but nothing came up. I have installed the base ISE WebPack for Linux...

0 21yrs

sjhill

0 21yrs sjhill

beginer

Hello, I've got some VHDL courses at university, i worked on rael time embedded design for years and i lost most of thi...

2 21yrs

e2ext

2 21yrs e2ext

Control asynchronous SRAM like synchronous SRAM

Hello, I've an Virtex II (later it'll be a Spartan 3) witch is connected to external asynchronous SRAM. Now I would lik...

3 21yrs

michaeldre

3 21yrs michaeldre

FPGA Boards

Link to a good selection of FPGA based boards http://www.hitechglobal.com/Boards/allboards.htm as well as IP Cores for F...

3 21yrs

ipcores

3 21yrs ipcores

Synplify 8.1 vs. Quartus II 5.0 QoR

Hi, Recently we are considering switching from Virtex II to Stratix II. We have evaluated both Synplify 8.1+ISE 7.1i wi...

6 21yrs

wcyeh_nospam

6 21yrs wcyeh_nospam

Incremental Compilation in Quartus 4.2

Hi, I've recently upgraded to Quartus 4.2 and discovered the Incremental Compilation feature. Has anyone had any proble...

2 21yrs

jjlindula

2 21yrs jjlindula

Incremental Comilation in Quartus 4.2

Hi, I've recently upgraded to Quartus 4.2 and discovered the Incremental Compilation feature. Has anyone had any proble...

0 21yrs

jjlindula

0 21yrs jjlindula

Hard Ethernet MAC for Virtex-4 FX12

Hi, I am trying to use V4 FX's hard EMAC core. (EDK's opb_ethernet_0 is soft core.) Has anyone ever made hard EMAC worki...

1 21yrs

zhg.liu

1 21yrs zhg.liu

Design flow of Spartan3 for my own embedded processor and HW logic?

I plan to combine my own embedded processor and HW logic into Spartan3. EDK just supports MicroBlaze or PowerPC, right?...

1 21yrs

yijun_lily

1 21yrs yijun_lily

Accessing BRAM as a SRAM

Hallo, I have a Spartan 3 Starter Board. I should use a BRAM as a SRAM. I have read that BRAM_if_controller should do i...

7 21yrs

marcotoschi_no_spam

7 21yrs marcotoschi_no_spam

Wrong type name (subtitution) in post-place & route simulation model.

Hi All. Having a module with input signal of my own type, described in package (which is simply "type MYTYPE is array i...

0 21yrs

al.lopich

0 21yrs al.lopich

Xilinx Parallel Cable III flying lead repair

The flying leads on my Xilinx Parallel Cable III won't last much longer (they are starting to break at the 9-way housin...

1 21yrs

leon.heller

1 21yrs leon.heller

compact flash configuration on ml403 board

hi can anyone expalin me how to use compact flah to configure the device with my design bit file. I tried to convert .b...

0 21yrs

kurapati77

0 21yrs kurapati77

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