Hi,
I try to find some information about the internal structure of the configuration-frames for Xilinx Virtex-II (Pro) architecture. On Xilinx websites I just find informations about the configuration-memory-addressing for these architectures and some informations for the Virtex architecture, but i`m intressted in the meaning of the bits in the frames. Can anybody help me?
At the moment I plan to use JBits and analyze the bitstream(s) afterwards, but this won`t be the best way.
thx, Sven
You won't find much (any?) official xilinx documentation about the meaning of individual bits in the frames. There are some tools you can use to reverse engineer for yourself, such as the "-l" switch to bitgen, the ngc2xdl, and so on.
This subject is/has been discussed at some length on the partial-reconfig mailing list - details here:
Googling a topic and adding the search term "partial-reconfig" often finds the list archive as well.
Hope this helps,
John
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