Hi,
I try to find some information about the internal structure of the configuration-frames for Xilinx Virtex-II (Pro) architecture. On Xilinx websites I just find informations about the configuration-memory-addressing for these architectures and some informations for the Virtex architecture, but i`m intressted in the meaning of the bits in the frames. Can anybody help me?
At the moment I plan to use JBits and analyze the bitstream(s) afterwards, but this won`t be the best way.
thx, Sven