Field-Programmable Gate Arrays

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FPGA I/O pin current sink

Could u please suggest me the Xilinx FPGA device I/O pin with around 150mA current sink/source capability. what is the n...
5 comments posted 21yrs
posted by sandasai
5 comments posted 21yrs posted by sandasai

Upgrading the EDK from 6.3

So, having had something of a forced absence from FPGA's for a few months, I've just been looking at upgrading to 7.1 f...
3 comments posted 21yrs
posted by news
3 comments posted 21yrs posted by news

Little Problem with EDK 7.1 (Errors while compiling)

Hi Everybody Actually I'm pretty new in using Xilinx software so can't yet fi these small troubles by myself. But anywa...
0 comments posted 21yrs
posted by dima_turbiner
0 comments posted 21yrs posted by dima_turbiner

board-level simulation?

Have any of you tried to simulate the pre-configuration startup conditions of an FPGA? Sometimes pins are tied high, ti...
0 comments posted 21yrs
posted by jhallen
0 comments posted 21yrs posted by jhallen

Xilinx ISE 7.1i

Hello, I am new to fpga design and am trying to use Webpack to generate a bit-file from an edif file preconverted by an...
0 comments posted 21yrs
posted by m_oylulan
0 comments posted 21yrs posted by m_oylulan

Sch & Layout Free Program

What is the best FREE Schematic & PCB Layout software available that will run on Windoze XP? I've looked at PCB123.com...
15 comments posted 21yrs
posted by ericjohnholland
15 comments posted 21yrs posted by ericjohnholland

Clock doubler to double an input 13.5 Mhz

Hi, I need to double an input clk of 13.5mhz to 27 mhz...but the DCM core in xilinx can take frequencies from 24 Mhz an...
12 comments posted 21yrs
posted by gmethi
12 comments posted 21yrs posted by gmethi

FPGA/CPLD trend

I had a question about the latest happening in this market. Since I am new in this area excuse me in advance if the que...
6 comments posted 21yrs
posted by learnfpga
6 comments posted 21yrs posted by learnfpga

Hope for OS X tools...

http://www.apple.com/pr/library/2005/jun/06intel.html Apple at to switch to using Intel procesors, presumably x86, for...
4 comments posted 21yrs
posted by christopher.saunter
4 comments posted 21yrs posted by christopher.saunter

Pissed off with Xilinx - Spartan 3

14 week lead time for samples for the XC3S200. How can you prototype with that? It makes worry even more when it comes t...
47 comments posted 21yrs
posted by Fred
47 comments posted 21yrs posted by Fred

Spartan 3 Starter kit group formed

I've just formed a Yahoo group for users of the Xilinx/Digilent Spartan 3 Starter Kit: http://groups.yahoo.com/group/s3...
7 comments posted 21yrs
posted by leon.heller
7 comments posted 21yrs posted by leon.heller

Generating linker script for Altera desgn

Hi I am a first time user of QuartusII + SOPC builder. After I create a design and map the different memories (external...
5 comments posted 21yrs
posted by shiladitya.biswas
5 comments posted 21yrs posted by shiladitya.biswas