Field-Programmable Gate Arrays

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Generating linker script for Altera desgn

Hi I am a first time user of QuartusII + SOPC builder. After I create a design and map the different memories (external...
5 comments posted 21yrs
posted by shiladitya.biswas
5 comments posted 21yrs posted by shiladitya.biswas

Microblaze 4.0 with uClinux is ok or not?

Hi help - please could somebody confirm if the latest uclinux kernel would work with EDK 7.1 made system using MicroBla...
4 comments posted 21yrs
posted by antti
4 comments posted 21yrs posted by antti

how to use FPU with EDK7.1i

Hi All, I used EDK7.1i to do some projects(Microblaze core), in the projects there are many floating point computing, s...
1 comments posted 21yrs
posted by lnzhao
1 comments posted 21yrs posted by lnzhao

Xilinx + ModelSim XE Linux

Hi all, I'm happy to see Xilinx is releasing their WebPack for Linux, and with a couple of minor tweaks, it actually wo...
3 comments posted 21yrs
posted by tmccoy
3 comments posted 21yrs posted by tmccoy

ORCAD CIS 7.2

Does anyone have experience with Orcad Express CIS 7.2? I am trying to creat an EDIF or EDN file that can be used in is...
0 comments posted 21yrs
posted by learnfpga
0 comments posted 21yrs posted by learnfpga

TI TMS320 DSP as a soft-processor in FPGA?

Hello to all! Does anyone know of a design involving a TI TMS320 DSP as a soft-processor in FPGA? I found the model of...
0 comments posted 21yrs
posted by bmscc
0 comments posted 21yrs posted by bmscc

*.mcs format file can't contain over 1Mbyte data?

It might be a silly question, but I want to make sure somthing. I got a description about *.mcs file like below -------...
1 comments posted 21yrs
posted by aw2310
1 comments posted 21yrs posted by aw2310

FPGA : MAC FIR doubt--HELP ME PLEASE

Hi I have used Coregnerator FIR filter in my desing. Initially i have used fixed coefficients, which is stored in BRAM...
7 comments posted 21yrs
posted by pbijoy
7 comments posted 21yrs posted by pbijoy

Xilinx ISE Webpack download problem

Hi I am new to FPGA and wanted to try out the ISE Webpack from Xilinx, I have registered at the site but when I try to...
0 comments posted 21yrs
posted by kundol30
0 comments posted 21yrs posted by kundol30

Query - ChipScope Pro analyzer

Hi , When I tried to use Chipscope Pro Analyzer for programming the V2Pro fpga . I was able to succesfully connect the...
1 comments posted 21yrs
posted by nkishorebabu123
1 comments posted 21yrs posted by nkishorebabu123

edk 6.3 : INTERNEL_ERROR

Hi, While taking my first steps with the EDK, I'm running into problems right away. - clean install of ISE 6.3i and EDK...
2 comments posted 21yrs
posted by xilinx
2 comments posted 21yrs posted by xilinx