board-level simulation?

Have any of you tried to simulate the pre-configuration startup conditions of an FPGA? Sometimes pins are tied high, tied-low, etc. Sometimes the chip comes out of reset before clocks are ready, etc. Sometimes the configuration logic is broken.

Board level bring-up with FPGAs always seems to require lab debugging of reset issues because these things are not normally properly simulated.

It would sure be nice if tool generated back-annotated netlist included the FPGA startup logic, or at least an approximation of it.

/* ( */               /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
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Joseph H Allen
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