Clock doubler to double an input 13.5 Mhz

Best way is PLL, but if not ....

Clock into one side of XOR. Output of XOR clocks D-type. Q of D type thru inverter to D and other input of XOR. Take doubled clock out of XOR output.

Bit naff but works.

Chuck

Only true if you use DLL outputs. For FX-only you can go down to 1.5 MHz IIRC.

Maybe. Is your input duty cycle 50%? Is it still 50% after the IBUF inside the part? Do you need a specific duty cycle on the doubled clock? Can you tolerate jitter on the doubled clock?

If your input has exactly 50% duty cycle you can create a relatively low-jitter doubled clock and it could be squared off by adjusting the delay to one leg of the XOR, or if the jitter is low enough by feeding through the DCM.

Hi Chuck,

Thanks for replying..

Did I get this right:

Take my 13.5 and give it as one input of an XOR

Take the output of the XOR1 and give it as input clk to a D-FF1

Take the output of the D-FF1 and give it as input to an inverter.

Take the output of the inverter and give it as input clk to another D-FF2

and also as the second input of the XOR1

And the output of the XOR1 gives 27mhz

Am I understanding this right?

Thank you, Methi

Chuck Bodgers wrote:

Hi Gabor,

Thanks fore replying.

"For FX-only you can go down to 1.5 MHz IIRC."

How do I do this?

I mean, how do I make use of the DCM core in Xilinx to take an input clk of 13.5mhz...

Thanks, Methi

Gabor wrote:

Methi,

CLKIN of the DCM is 13.5 MHz from a clock input.

Do not connect anything to CLKFB, CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X_b, or CLKDV.

Use the CLKFX or CLKFX_b outputs with M=2, D=1.

This selects only the use of the synthesizer, and the low frequency restriction becomes as low as 1 MHz for CLKIN.

CLKFX must still be greater than 24 MHz, which is OK, because 13.5 X 2 = 27 MHz.

Aust> Hi Gabor,

Yes

Yes

Yes

No, take it to the D input of the DFF1 - there is only one XOR and one DFF in design.

Yes

Yes, but it does rely on your 13.5MHz input being 50% duty cycle. The output will be a positive pulse produced on each edge of input, the pulse width being a function of the prop delays on XOR/DFF and inverter.

I hope the above makes it clearer - a picture is worth a thousand words!!!!

Ciao for now

Chuck

Hi Austin and Chuck,

Thankyou so much for helping me out...

I am goin to try using the DCM core

as well the XOR circuitry( by the way, I found the diagram in one of the google posts)

Thank you so much for your time..

I really appreciate all the help..

Methi

Chuck Bodgers wrote:

Hello Chuck, Gabor and Austin..

I used both the methods...and have a 27 Mhz for both of these methods..

Thankyou very much for helping me out..

I appreciate it very much,

Methi

methi wrote:

"Chuck Bodgers" schrieb im Newsbeitrag news:42a4a6d7$0$1694$ snipped-for-privacy@ptn-nntp-reader04.plus.net...

Before I would use a XOR-doubles clock inside a nowadays FPGA/CPLD for a real product (not just lab stuff), I would rather try a cheap VCO based PLL.

Regards Falk

"Austin Lesea" schrieb im Newsbeitrag news:d82bln$ snipped-for-privacy@cliff.xsj.xilinx.com...

Maybe it should be noted that when using the DCM, the input clock has to match some tight jitter specification. If the 13.5 MHz clock comes from a lousy RC-oscillator, it wont work reliable.

Regards Falk

There are two ways to do this:

(1) Use DCM with CLKFX output, DO NOT USE DLL outputs, as they limit you to

24 MHz. (2) There is a nice circuit which doubles any frequency using a delay buffer

• XOR.

If you REALLY want to go for it (it's working, but ...), just say it. Hope this helps.

Vladislav

Methi,

You cannot use any DLL outputs, such as CLK0 and CLK2x, as they limit your lowest CLKIN to 24 MHz.

Use only CLKFX or CLKFX180 outputs, NOTHING ELSE.

Try this and let's know how's going.

Vladislav