Field-Programmable Gate Arrays

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Xilinx Powe Requirements V2PRO complaint

I'm designing with a V2PRO and its config PROM. I noticed that I will need: 1. VCCint (PROM) = 1.8V 2. VCCint (FPGA) =...
3 comments posted 21yrs
posted by robnstef
3 comments posted 21yrs posted by robnstef

problems with Xilinx GSRD design for ML403

Hi All I just tried GSRD design for ML403 from Xilinx web site Did smbd in Xilinx make final test at all I'm using ISE7...
0 comments posted 21yrs
posted by leevv
0 comments posted 21yrs posted by leevv

Commercial Z180 / 64180 core

Hi, Is anyone aware of a real (that is -- actually available) Z180 or 64180 core where the peripherals have all (or eve...
2 comments posted 21yrs
posted by gavin.melville
2 comments posted 21yrs posted by gavin.melville

User Core to PLB Bus example for Virtex 2P in EDK.

Does anyone has an example of a user IP core hooked up to the PLB bus for a Virtex 2P in EDK? I am wondering how I can...
1 comments posted 21yrs
posted by nrivera.eng
1 comments posted 21yrs posted by nrivera.eng

Serial I/O - Delay Output

I am generating a slow serial data stream in response to a input clock. I need to delay n uSec's after detecting the cl...
3 comments posted 21yrs
posted by
3 comments posted 21yrs posted by

Need some help with understanding MDM

Hello, I am not getting a clear undertsanding of the debugging part of microblaze. I tried reading many docs. but i don...
1 comments posted 21yrs
posted by kittyawake
1 comments posted 21yrs posted by kittyawake

Virtex 4 and reconfigurable computer

Hi! I would like to know if the Xilinx Virtex 4 offer the possibility of partially reconfigure bitstreams directly (as...
2 comments posted 21yrs
posted by taileb.mehdi
2 comments posted 21yrs posted by taileb.mehdi

DES core for Xilinx Virtex 2Pro for the EDK and PLB

Does anyone know were I can get a DES core for the Xilinx EDK the Target is the Virtex 2 Pro? I need this core to inter...
1 comments posted 21yrs
posted by nrivera.eng
1 comments posted 21yrs posted by nrivera.eng

reading file from CF with 4VSX35 and EDK

Hi, I am trying to read file from CF using SysAceMPU with a V4SX35 fpga on a ML402 board. I have connected the MPA, MPD...
0 comments posted 21yrs
posted by krishna_tvkc
0 comments posted 21yrs posted by krishna_tvkc

Need help understanding this AHDL code

Hi, I have some questions regarding the following piece of code... In the AHDL code, the following variable is declared...
2 comments posted 21yrs
posted by gmethi
2 comments posted 21yrs posted by gmethi

Frequency divisors

In my project, which uses an Altera Cyclone EP1C12, I need to generate a lot of different frequencies, such as f=10Mhz,...
5 comments posted 21yrs
posted by spammalatuamamma
5 comments posted 21yrs posted by spammalatuamamma

Need help with AHDL

Hi, I have some questions regarding the following piece of code... In the AHDL code, the following variable is declared...
0 comments posted 21yrs
posted by gmethi
0 comments posted 21yrs posted by gmethi