Latest threads in Field-Programmable Gate Arrays

disappointed with Altera this time

hi Altera is the one that likes to claim many things, one of those was that Altera was the first PLD vendor supporing I...

1 21yrs

antti

1 21yrs antti

ppc 405 in debug halt mode

Hi all, Iam using ml310 board and in my design Iam using two PPC 's. To my needs I want to collect the addresses of the...

7 21yrs

reddy.jagadeesh

7 21yrs reddy.jagadeesh

Setting ucf for DLLs:Urgent

Hi All, can some one guide me setting ucf for DLLs.I am using clkx2,clkx4,clkx8.The board I am suing is spartan 2 FPGA,...

1 21yrs

sri_poddaturu

1 21yrs sri_poddaturu

FPGAs and JTAG

Hi All, I am stuck with some JTAG interconnection tests on a board with 9 Xilinx V2Pros and 2 Altera Stratixs. I am usi...

0 21yrs

adarsh.jain

0 21yrs adarsh.jain

Difficult in probing through chipscope

Hello Guys, I am finding difficult in probing virtex 2pro using chipscope. I am using chipscope pro logic inserter. I h...

2 21yrs

stud_lang_jap

2 21yrs stud_lang_jap

FPGAs in Cray XD1

Hi: I am going to work with FPGAs inside the Cray XD1. My question is, wether there exists an implementation of the Cra...

0 21yrs

aernst

0 21yrs aernst

Area_Group

Hello, I made an Entity with an Process using Xilinx 7.1 . Then made: GEN_A : GenInt port Map ( clk_prg_i => clk_prg_i...

2 21yrs

Nightstorm

2 21yrs Nightstorm

choosing an fpga board

Hi all! I'm starting a PhD project in the field of design of SoC systems on FPGA. I would like to buy an FPGA board wit...

9 21yrs

taileb.mehdi

9 21yrs taileb.mehdi

DC vhdl question

Hello, A customer of ours is using one of our IPs and reports that DC (for synthesis) complains about two things : *A*...

2 21yrs

_no_spa_m_info_no_underscore_

2 21yrs _no_spa_m_info_no_underscore_

Low cost altera board

Came across this http://www.terasic.com/english/fpga_01.htm Just wondering if anyone has one or has tried one? Designed...

3 21yrs

news

3 21yrs news

Altera Net Seminar on 3GPP Release 6 and Beyond

Join Altera's free net seminar, Addressing Base Station Design Challenges for 3GPP Release 6 and Beyond. You will find...

0 21yrs

deepak100

0 21yrs deepak100

dru files for eagle ?

Hi, Iam designing a little cpu board with an fbga-289-14x14 chip. Where can i get a dru file for eagle, so i can design...

6 21yrs

unknown

6 21yrs unknown

[XILINX][V2PRO]IOB tristate pins.

So, the IOB in V2PRO has two tristate pins, T1 and T2. As far as I can tell, they're interchangeable in standard, i.e....

2 21yrs

symon_brewer

2 21yrs symon_brewer

JTAG port access in Cyclone

hello Is there any example of how to add JTAG port support into own non-SOPC builder design like I can directly access...

12 21yrs

me

12 21yrs me

TDM over Aurora

Guys I'm trying to Time Division Multiplex virtual channels onto a rocketio system that is allready using Aurora. Every...

1 21yrs

weston_katherine

1 21yrs weston_katherine

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