Field-Programmable Gate Arrays

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ppc 405 in debug halt mode

Hi all, Iam using ml310 board and in my design Iam using two PPC 's. To my needs I want to collect the addresses of the...
7 comments posted 21yrs
posted by reddy.jagadeesh
7 comments posted 21yrs posted by reddy.jagadeesh

Setting ucf for DLLs:Urgent

Hi All, can some one guide me setting ucf for DLLs.I am using clkx2,clkx4,clkx8.The board I am suing is spartan 2 FPGA,...
1 comments posted 21yrs
posted by sri_poddaturu
1 comments posted 21yrs posted by sri_poddaturu

FPGAs and JTAG

Hi All, I am stuck with some JTAG interconnection tests on a board with 9 Xilinx V2Pros and 2 Altera Stratixs. I am usi...
0 comments posted 21yrs
posted by adarsh.jain
0 comments posted 21yrs posted by adarsh.jain

Difficult in probing through chipscope

Hello Guys, I am finding difficult in probing virtex 2pro using chipscope. I am using chipscope pro logic inserter. I h...
2 comments posted 21yrs
posted by stud_lang_jap
2 comments posted 21yrs posted by stud_lang_jap

FPGAs in Cray XD1

Hi: I am going to work with FPGAs inside the Cray XD1. My question is, wether there exists an implementation of the Cra...
0 comments posted 21yrs
posted by aernst
0 comments posted 21yrs posted by aernst

Area_Group

Hello, I made an Entity with an Process using Xilinx 7.1 . Then made: GEN_A : GenInt port Map ( clk_prg_i => clk_prg_i...
2 comments posted 21yrs
posted by Nightstorm
2 comments posted 21yrs posted by Nightstorm

choosing an fpga board

Hi all! I'm starting a PhD project in the field of design of SoC systems on FPGA. I would like to buy an FPGA board wit...
9 comments posted 21yrs
posted by taileb.mehdi
9 comments posted 21yrs posted by taileb.mehdi

DC vhdl question

Hello, A customer of ours is using one of our IPs and reports that DC (for synthesis) complains about two things : *A*...
2 comments posted 21yrs
posted by _no_spa_m_info_no_underscore_
2 comments posted 21yrs posted by _no_spa_m_info_no_underscore_

Low cost altera board

Came across this http://www.terasic.com/english/fpga_01.htm Just wondering if anyone has one or has tried one? Designed...
3 comments posted 21yrs
posted by news
3 comments posted 21yrs posted by news

Altera Net Seminar on 3GPP Release 6 and Beyond

Join Altera's free net seminar, Addressing Base Station Design Challenges for 3GPP Release 6 and Beyond. You will find...
0 comments posted 21yrs
posted by deepak100
0 comments posted 21yrs posted by deepak100

dru files for eagle ?

Hi, Iam designing a little cpu board with an fbga-289-14x14 chip. Where can i get a dru file for eagle, so i can design...
6 comments posted 21yrs
posted by unknown
6 comments posted 21yrs posted by unknown

[XILINX][V2PRO]IOB tristate pins.

So, the IOB in V2PRO has two tristate pins, T1 and T2. As far as I can tell, they're interchangeable in standard, i.e....
2 comments posted 21yrs
posted by symon_brewer
2 comments posted 21yrs posted by symon_brewer

JTAG port access in Cyclone

hello Is there any example of how to add JTAG port support into own non-SOPC builder design like I can directly access...
12 comments posted 21yrs
posted by me
12 comments posted 21yrs posted by me

TDM over Aurora

Guys I'm trying to Time Division Multiplex virtual channels onto a rocketio system that is allready using Aurora. Every...
1 comments posted 21yrs
posted by weston_katherine
1 comments posted 21yrs posted by weston_katherine

nios2 / terminal

Hi, Do you have experience with nios2 and a specific terminal (hyperterminal, tera pro, or others) ?. I have problem to...
1 comments posted 21yrs
posted by bhb22l
1 comments posted 21yrs posted by bhb22l