Field-Programmable Gate Arrays

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experiences with Summit Visual Elite

has anyone used Summit's Visual Elite tool to do schematic/HDL based design, how does this compare with other tools. I...
0 comments posted 21yrs
posted by wallge
0 comments posted 21yrs posted by wallge

Maintaining a Pipeline

I see two issues here looking for the classical design practices. Consider a solution space scanner feeding a N-stage p...
3 comments posted 21yrs
posted by spam
3 comments posted 21yrs posted by spam

Cant' make SignalTap works...

hello, I use an APEX 20k1000c. I insert nodes for signaltap, re-compile it and now the only things i have is "post-trig...
3 comments posted 21yrs
posted by gbirot
3 comments posted 21yrs posted by gbirot

FPGA for video processing

Hi All, I'm after a piece of FPGA or DSP-based hardware for the purposes of performing real time video processing on di...
5 comments posted 21yrs
posted by dave.m.moore
5 comments posted 21yrs posted by dave.m.moore

FPGA PC104 development board

Hello Everybody ! I have looking for FPGA PC104 development board for some time. I like to buy PC104 development board...
4 comments posted 21yrs
posted by sinebrate
4 comments posted 21yrs posted by sinebrate

multiprocessing with microblaze ?

Anyone have experience putting multiple microblaze's in a single FPGA ?? Is it practical to put 2/4/8 processors in a si...
2 comments posted 21yrs
posted by sja
2 comments posted 21yrs posted by sja

Spartan ii Slave Serial programming

Hi there, I am having trouble with Xilinx Webpack 7.1i, trying to program a chain of 2 Spartan II FPGA's in slave seria...
0 comments posted 21yrs
posted by abeaujean
0 comments posted 21yrs posted by abeaujean

vsync on dvi

Hi, I have built a dvi to lvds converter. However the picture still flickers and is off by 1 pixel. I think I am having...
3 comments posted 21yrs
posted by benjamin
3 comments posted 21yrs posted by benjamin

Two Verilog FSM style compare

Hi all, There is a problem on How to write FSM in Verilog(http://www.asic-world.com/tidbits/verilog_fsm.html). Most syn...
9 comments posted 21yrs
posted by zhushenli
9 comments posted 21yrs posted by zhushenli

unisim for synthesis?

dear i am using 'unisim' for Xilinx component for VHDL "simulation" in Modelim. So, as far we know the name of the comp...
2 comments posted 21yrs
posted by pasacco
2 comments posted 21yrs posted by pasacco

good bye nios (o;

Finally... The last 4 days working with NIOS2 since I can't upgrade my subscription... ...or is there an opensource alte...
10 comments posted 21yrs
posted by me
10 comments posted 21yrs posted by me