This is really a question for the synthesis tools on the matter of how your code is interpreted. If any of the coding styles would produce different results, the corresponding synthesis tool should have fixed this deficiency by now :)
However, there is no really benefit in terms of what you will eventually get, but rather what is more convenient. Personally, I always prefer a single "always", especially if the state machine has MANY outputs.
Going a bit further than your question, in my group, I am not enforcing any of those ways. The coding style is completely at the designer's choice. Instead, I enforce the designer to very-well document the "bubbles" stuff, so that he knows what this state machine is doing and it is coded only once.
I know someone who never ever makes more than one assignment to a variable in a single always block (no defaulting at all for maximized typing). Instead he makes an assignment to each register in each decision branch, so that you get one decision branch or less per editor screen: tiny state machines end up being 10,000 lines. He also uses non-blocking assigns in combinatorial always blocks, which is just weird. He also does the out of order thing above: there will be some code at the end whose outputs are used by a state machine case at the top. Finally, he never uses "if": only "casex", always with "// synthesis full_case parallel_case". Usually, the casex's are three levels deep. Finally he always uses positional arguments in instantiations for modules with 100s of signals (sometimes the wire names even match the port names). Oh yeah: he never uses parameters- only `defines all in one giant include file, even for state machine states. There is not one comment in 100,000 lines of code. I am not making this up.
Hmm... should I just edit the code and get it over with or should I make that Verilog refactoring program I always knew would come in handy... hmm...
Well on the positive side, his_signals_look_like_this, NotLikeThis. He uses the default emacs verilog mode, so the begins and ends are at the same indentation level. Some other person's annoying code looks like this:
if (theSignal) begin stuff end // if (theSignal)
Whoever wrote the elisp macros which put in these useless VHDLish comments should be shot. His files all begin with a long boilerplate comment with no useful information (but he does put comments in his code, unlike the first person).
Sorry, I'll stop ranting now.
/* email@example.com (126.96.36.199) */ /* Joseph H. Allen */