Field-Programmable Gate Arrays

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Chess & FPGAs

looks like Chess and FPGAs are making news all around, esp Hydra, Alphadata, and xcell article http://www.xilinx.com/pu...
3 comments posted 21yrs
posted by johnjakson
3 comments posted 21yrs posted by johnjakson

interfacing to multiple converters

Hi, I need to interface 2 ADCs and 1 DAC to a Spartan-II FPGA running at 57.6MHz. My data (12-bits wide) needs to be sa...
4 comments posted 21yrs
posted by m_oylulan
4 comments posted 21yrs posted by m_oylulan

Updating FPGA SPROM firmware over the IP network?

Hi, I want to know if there is a method of loading/updating firmware into an SPROM using the network. Rather than physi...
0 comments posted 21yrs
posted by andrewl
0 comments posted 21yrs posted by andrewl

Memory Controller and State Machine

Hallo, I'm trying to create a memory controller based on a state machine to send to Microbalze signals like ram_data_ou...
1 comments posted 21yrs
posted by marcotoschi
1 comments posted 21yrs posted by marcotoschi

State of unused pins in Spartan II.

Hi, What is a state of unused pins in SpartanII device? Is this high impedance state? Best Regards Krzysztof Przednowek
1 comments posted 21yrs
posted by nospam
1 comments posted 21yrs posted by nospam

doubt regarding code generator

Hello everyone, I have generally been using the xilinx CoreGenerator for some specified components. My query is , can i...
0 comments posted 21yrs
posted by anil.janumpally
0 comments posted 21yrs posted by anil.janumpally

V4 and DDR2 666

Hi all, Xilinx has announced support for DDR2 up to 533 MHz. Are there any physical limitations that won't allow higher...
2 comments posted 21yrs
posted by fortiz80
2 comments posted 21yrs posted by fortiz80

FPGA vs. ASIC vs. Processor

Hi all, I'm doing a project on "VHDL implementation of LOG CFAR". I need somebody to enumerate the differences FPGA vs....
2 comments posted 21yrs
posted by praveen.rajaretnam
2 comments posted 21yrs posted by praveen.rajaretnam

LVTTL Spec

Quick question: Anyone know who set the LVTTL spec if there is such a defined spec. As in, IEEE, ANSI, TIA, EIA, etc......
1 comments posted 21yrs
posted by kevin
1 comments posted 21yrs posted by kevin

PLB registers

Hi I have a small question. I have a PLB Peripheral with "Software Addressable Registers". Say the baseaddress of my pe...
2 comments posted 21yrs
posted by johnsons
2 comments posted 21yrs posted by johnsons

Spartan-3e order of availability?

Can anyone in the know comment on what the likely order of availability of Spartan-3e parts (in sub-1000 piece quantiti...
11 comments posted 21yrs
posted by eric
11 comments posted 21yrs posted by eric

Need help for Xilinx FPGA

Hi, The volunteer CPCNG Design Team is working on a family computer based on eZ80 CPU. We have designed a board (eurobo...
6 comments posted 21yrs
posted by ChristopheGuelff
6 comments posted 21yrs posted by ChristopheGuelff