Rising to falling edge constraints on Actel ProAsic

I have some problems with constraining logic that is using two clocks. I have logic that uses two clocks, GLB (48 MHz, 20.83ns) and GLA (96 MHz, 10.416 ns). Also I use rising and falling edges of 96 MHz clock. What I need is to constraint this logic not only rising 48 to rising

96 but also rising 48 to falling 96. As I know there is no possibility in Designer software to use rising and falling edge constraints. Please tell me this is not true!!!

Anyway, what I did is that I used clock to clock constraint in the .sdc file in the following way:

set_max_delay 5.2085 -from [get_clocks {clock_comp_1/Core:GLB}] -to [get_clocks {clock_comp_1/Core:GLA}]

because I want to constraint rising 48 MHz to falling 96Mhz to

5.2085ns. But, this also presumes that rising 48 MHz to rising 96Mhz is also 5.2085 and I dont need this. This has to be 10.416 ns.

Does anyone know how to solve this?

Thx, Jura

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