Latest threads in Field-Programmable Gate Arrays

SELV - power supply specification

Hello i bought a development board frm the ARM. It says that for safety use SELV (safety extra low power supply). Whats...

4 21yrs

vssumesh_asic

4 21yrs vssumesh_asic

Problems with Timing Simulation

Hi, I have performed a functional simulation and static timing analysis of my design. Both are OK. But when trying to p...

6 21yrs

ALuPin

6 21yrs ALuPin

about fast adder

I'm interested in the implementation of a fast adder for 32 bit data. The CLA is too expensive so I'm searching for som...

11 21yrs

giovanniparodi79

11 21yrs giovanniparodi79

Actel vs. Xilinx and Altera

Hi, It's been a couple of years since I've been a heavy FPGA user, but it appears that I'll now be getting back into th...

3 21yrs

JKolstad71HatesSpam

3 21yrs JKolstad71HatesSpam

Has anybody run Virtex-4 FPGAs at 300MHz+ interface speed?

I was trying to determine the max frequency that can be clocked thru the Virtex-4 FPGA pins. While referring the Virtex...

2 21yrs

azamirfan

2 21yrs azamirfan

for sale: two spartan-3 dev boards, $50 each (normally $100)

I have two Spartan-III development boards; I bought two of Xilinx's dev kits a while ago and no longer need them. Here'...

0 21yrs

megacz

0 21yrs megacz

PC104 (ISA) bus in FPGA (Spatan 2E)

Hello! Currently I design FPGA design which will have pc104(ISA) bus. First at all I cannot find detailed ISA bus speci...

3 21yrs

sinebrate

3 21yrs sinebrate

Cheking out Linux Kernel Source

Hello, I am using VIIPro on ML310 board, and trying to port Linux on it. While I was trying to check out the Linux Kern...

2 21yrs

weese

2 21yrs weese

Spartan3 pci above 33MHz

There was a thread with this subject line last September. Steve Knapp from Xilinx responded in the thread as follows: "...

1 21yrs

rsefton

1 21yrs rsefton

Spartan II 2s200 PCI Board

Hi everyone, I recently bought a Spartan II 2s200 PCI Board to use in a project. I programmed it with the Opencores PCI...

2 21yrs

jtrabal

2 21yrs jtrabal

Triggering and reseting FF

hello all, i have some doubt on the timing specs of FF set and rests. I wrote the folllowing code in verilog. always @(p...

2 21yrs

vssumesh_asic

2 21yrs vssumesh_asic

virtex4 evaluation board

hi all, since my company is going to buy a board from silica based on the virtex4 fpga (the part number is ADS-XLX-V4LX...

2 21yrs

sabatian

2 21yrs sabatian

Program from external memory

Hi Here I would like to need some guidelines. I have a design which takes up 38 out of the 44 BRAMS available in my chi...

7 21yrs

johnsons

7 21yrs johnsons

PowerPC interrupt

Hallo everyone. I have a simple ( but strange) problem. I am making a PLB interface for a decoder and I would like to i...

4 21yrs

johnsons

4 21yrs johnsons

EDK/ISE 7.1 SmartModel Set-up Issue with ModelSim 6.0a

Hi, I'm using ModelSim SE 6.0a with ISE 7.1 (SP 2) and EDK (SP 1). I get the following error with the PPC SmartModel. #...

5 21yrs

njoroge

5 21yrs njoroge

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