Hi
Here I would like to need some guidelines. I have a design which takes up 38 out of the 44 BRAMS available in my chip (VirtexIIPro, with one PowerPC). Now I would like to know how I can run the program without using the debugger. Can anybody give me an idea. If there are any tutorials available, I will really happy.
Thank you all, Joey
I forgot to mention something.. I have 32MB SDRAM and 2 PROMs available on my board !! I have an ACE connector, but no card :(
"Joey" schrieb im Newsbeitrag news:dag8ua$8f5$ snipped-for-privacy@news.uni-kl.de...
38available,
Hi,
do you want to run the program out of sdram or out of the bram? What is the size of the c-code? Do you use the edk system as top level? Or do you integrate the edk system in your own top level?
The tool flow from edk supports the mechanism to fit the c-code -> elf-file in the bram during the bitgen procedure.
Then when the fpga is loaded the c-code starts directly.
Hi,
I want to run the program from SDRAM. The .elf file is almost 117kB in size. And my program (text part) is more than 35kb in size. It will get even bigger later :( By the way, I am using XPS for the synthesis.
"Andi" schrieb im Newsbeitrag news: snipped-for-privacy@webx.sUNCHnE...
the size of the c-code? Do you use the edk system as top level? Or do you integrate the edk system in your own top level?
elf-file in the bram during the bitgen procedure.
Hi,
to add the c-code in sdram you need to store it in flash and build a booter that runs in the bram of the fpga to get the code out of the flash into the sdram and start it there. Do you have flash on your board?
The biggest "one" section with edk is 125 kb with several block rams. So you can store you whole project also in the bram of the fpga if you want to.
Since you have System ACE CF in your system that is the easiest way to load both bitstream and ELF file. Please read up in the EDK documentation how to generate an ACE file for your system.
- Peter
Andi wrote:
size of the c-code? Do you use the edk system as top level? Or do you integrate the edk system in your own top level?
the bram during the bitgen procedure.
I dont have a ACE CF on my board. Well, I have the ACE connector, but no card reader/card
"Peter Ryser" schrieb im Newsbeitrag news: snipped-for-privacy@xilinx.com...
the size of the c-code? Do you use the edk system as top level? Or do you integrate the edk system in your own top level?
elf-file in the bram during the bitgen procedure.
I have no CF card reader. But I have 2 PROMs on my board, and I would like to store the progam there.
If all I have is 6 block RAMs remaining, is it possible at all, to run the program on this board. My design uses up 38 out of the 44 BRAMs available. Can you advice me a possible solution.
"Peter Ryser" schrieb im Newsbeitrag news: snipped-for-privacy@xilinx.com...
the size of the c-code? Do you use the edk system as top level? Or do you integrate the edk system in your own top level?
elf-file in the bram during the bitgen procedure.
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