hello all, i have some doubt on the timing specs of FF set and rests. I wrote the folllowing code in verilog.
always @(posedge clk) if (a == 0) b
Triggering and reseting FF
Jul 06, 2005
2 Replies
Well....
First, let me ask "why"? What's the logic functionality you are after?
Second, what you are doing is driving a net from two different processes, which unacceptable by the synthesis tool. try replacing two last processes into one as following:
always @(posedge clk or posedge b) begin if (b) c i have some doubt on the timing specs of FF set and rests.
hi Vladislav, very sorry for not responding to your suggestions. it worked just fine. thank you very much for that. Actualy it was my mistake. thank you once again. regrds sumesh
Join the Discussion
Have something to add? Share your thoughts — no account required.
Didn't find your answer?
Ask the community — no account required