Field-Programmable Gate Arrays

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fastest FPGA speed grade?

Is the Xilinx Virtex 4 the fastest FPGA available in in-circuit reprogrammable format? Their data sheet claims 450MHz P...
19 comments posted 21yrs
posted by starfire151
19 comments posted 21yrs posted by starfire151

VHDL Clock Domains

Hello group, I am attempting to get data (column_in) from a fast clock domain(clk_wr) to a slow clock domain(clk_rd). I...
6 comments posted 21yrs
posted by bradsmallridge
6 comments posted 21yrs posted by bradsmallridge

Stratix open-drain pins

Hi, Anyone know if I can configure the output pins of a Stratix FPGA to be open-drain? I need open-drain outputs to inte...
5 comments posted 21yrs
posted by ernielin
5 comments posted 21yrs posted by ernielin

VPR fundaes

I need more information wirelength results given by VPR for ex: Wirelength results (all in units of 1 clb segments): To...
3 comments posted 21yrs
posted by k.najeeb
3 comments posted 21yrs posted by k.najeeb

PS/2 interface

I have two fpga boards; one of them pretends to be the device (say a mouse), the other one would be the host. I would l...
4 comments posted 21yrs
posted by greenplanet
4 comments posted 21yrs posted by greenplanet

Connecting ADC to Opb_Spi core

Hallo, I'm trying to connect a Spi 16 bit ADC to Opb_Spi core. Where I could find some software examples? I have made s...
7 comments posted 21yrs
posted by marcotoschi
7 comments posted 21yrs posted by marcotoschi

Virtex-2 Pro: Configuration Frames

Hi, i try to build a dynamic reconfiguration application with use of icap and the embedded powerpc. By reverse engineer...
2 comments posted 21yrs
posted by sven-habermann
2 comments posted 21yrs posted by sven-habermann

Ethernet FPGA development board

Hi there, This is my first post, so my apologies if this is inappropriate. I have designed an FPGA dev. board with an A...
2 comments posted 21yrs
posted by jai.dhar
2 comments posted 21yrs posted by jai.dhar

nios2 toolchain sources...

Evening... The NIOS2 sources are only available on the shipped CD's..right? So...then the downloadble NIOS2 evaluation v...
8 comments posted 21yrs
posted by me
8 comments posted 21yrs posted by me

EDK 6.3, Xilinx ML40x ML402, XBD files

Hi All Does anybody know if an XBD file is available for the Xilinx ML402 board? I'm currently using EDK6.3 - I'd also...
3 comments posted 21yrs
posted by allan
3 comments posted 21yrs posted by allan

Call for FPGAworld 2005

The FPGAworld Conference addresses all aspects of digital and hardware/software system engineering on FPGA technology....
0 comments posted 21yrs
posted by david
0 comments posted 21yrs posted by david

Xilinx IOB flop mapping vs. -bp switch

A question for the Xilinx guru's out there: I am experimenting with the map -bp switch (map slice logic) in order to ma...
1 comments posted 21yrs
posted by schellho
1 comments posted 21yrs posted by schellho

DDR controller : problems about burst access

I recently tried out DDR controller design from Xilinx(xapp608), and found it does not work properly during simulation...
0 comments posted 21yrs
posted by
0 comments posted 21yrs posted by

xapp 482 and add custom function

Hi, there I am a newbie in fpga area. I have a question about xps 6.3 mapper I am creating a project file based on xapp...
0 comments posted 21yrs
posted by im.de
0 comments posted 21yrs posted by im.de