Latest threads in Field-Programmable Gate Arrays

EDK/ISE 7.1 SmartModel Set-up Issue with ModelSim 6.0a

Hi, I'm using ModelSim SE 6.0a with ISE 7.1 (SP 2) and EDK (SP 1). I get the following error with the PPC SmartModel. #...

5 21yrs

njoroge

5 21yrs njoroge

fastest FPGA speed grade?

Is the Xilinx Virtex 4 the fastest FPGA available in in-circuit reprogrammable format? Their data sheet claims 450MHz P...

19 21yrs

starfire151

19 21yrs starfire151

VHDL Clock Domains

Hello group, I am attempting to get data (column_in) from a fast clock domain(clk_wr) to a slow clock domain(clk_rd). I...

6 21yrs

bradsmallridge

6 21yrs bradsmallridge

Stratix open-drain pins

Hi, Anyone know if I can configure the output pins of a Stratix FPGA to be open-drain? I need open-drain outputs to inte...

5 21yrs

ernielin

5 21yrs ernielin

Spartan-3E, ISE 7.1 some issues - solved (BUFG insertion problem)

Hi I think some others have seen this problem with ISE 7.1 as well, the 'auto BUFG' insertion logic is changed from 6.3...

2 21yrs

antti

2 21yrs antti

VPR fundaes

I need more information wirelength results given by VPR for ex: Wirelength results (all in units of 1 clb segments): To...

3 21yrs

k.najeeb

3 21yrs k.najeeb

PS/2 interface

I have two fpga boards; one of them pretends to be the device (say a mouse), the other one would be the host. I would l...

4 21yrs

greenplanet

4 21yrs greenplanet

Connecting ADC to Opb_Spi core

Hallo, I'm trying to connect a Spi 16 bit ADC to Opb_Spi core. Where I could find some software examples? I have made s...

7 21yrs

marcotoschi

7 21yrs marcotoschi

Virtex-2 Pro: Configuration Frames

Hi, i try to build a dynamic reconfiguration application with use of icap and the embedded powerpc. By reverse engineer...

2 21yrs

sven-habermann

2 21yrs sven-habermann

Ethernet FPGA development board

Hi there, This is my first post, so my apologies if this is inappropriate. I have designed an FPGA dev. board with an A...

2 21yrs

jai.dhar

2 21yrs jai.dhar

nios2 toolchain sources...

Evening... The NIOS2 sources are only available on the shipped CD's..right? So...then the downloadble NIOS2 evaluation v...

8 21yrs

me

8 21yrs me

EDK 6.3, Xilinx ML40x ML402, XBD files

Hi All Does anybody know if an XBD file is available for the Xilinx ML402 board? I'm currently using EDK6.3 - I'd also...

3 21yrs

allan

3 21yrs allan

Call for FPGAworld 2005

The FPGAworld Conference addresses all aspects of digital and hardware/software system engineering on FPGA technology....

0 21yrs

david

0 21yrs david

Xilinx IOB flop mapping vs. -bp switch

A question for the Xilinx guru's out there: I am experimenting with the map -bp switch (map slice logic) in order to ma...

1 21yrs

schellho

1 21yrs schellho

DDR controller : problems about burst access

I recently tried out DDR controller design from Xilinx(xapp608), and found it does not work properly during simulation...

0 21yrs

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