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PC104 (ISA) bus in FPGA (Spatan 2E)

Hello!

Currently I design FPGA design which will have pc104(ISA) bus. First at all I cannot find detailed ISA bus specification on Internet (I think for free). Also PCI to ISA bus bridge(national: CS5530) which is located on processor card (that I use) and generate PC104 timing does not contain any useful information in datasheet.

I read on this forum a lot about ISA bus and I am little confused :)... if ISA bus signals are synchronized on ISA bus clock or are received and transmitted on (rising ?)edge of IOR# and IOW# signals. Also I am not sure If I need address latch signal (BALE) or I can latch address bus on IOR# and IOW# signals???

I see example:

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and it is all synchronized to PC104 clock signal...... Is it only special case??

In my design FPGA must act as slave on ISA bus and should support 8-bit and 16-bit I/O mode and DMA.

So my question is where I can get detailed ISA bus specification (free :)) and how much this specification are depend on devices.. I think setup time, hold time... How is better to implement PC104 bus design sync or async? (Here I also have in mind possible problems with async design if i change FPGA)

Thank you and regards,

AMIR

Reply to
amko
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I don't know about "free", but I've always referred to "ISA and EISA Theory and Operation" by Ed Solari (Anabooks). This goes into considerable detail about real usage of the ISA bus including common mis-usage you may need to design around. It also contains EISA stuff which is more amusing than useful since PCI came out.

Also by Ed Solari: "AT bus design: Compatible with IEEE P996, 8 and 16 bit ISA, E-ISA, and EISA design"

Or this > Hello!

Reply to
Gabor

Hi Amir,

When I did my masters project a while back I did have some good use of ISA System Architecture by Tom Shanley and Don Anderson. They've also writen a book on EISA. You should be able to find it in almost any academic engineering library. If you need a review on the timing details of a standard 16-bit I/O device ISA cycle you can have a look in my report:

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I didn't look anything into DMA though, but the book I mentioned covers that.

/Johan

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Reply to
Johan Bernspång

I would not depend on ISA clock synchronization with control signals at all. Not only is the timing of the clock relative to the strobes not guaranteed, the signals are often too 'dirty' for use as a clock.

What we do for our PC/104 FPGA cards is use a high speed synchronous clock to the FPGA (50 or 100 MHz), not using any PC/104 signal as a clock. Then use edge detection on the write strobes to determine when to latch inputs The read path can be asynchronous (just enabling the output buffer with the read strobe)

Peter Walllace

Reply to
Peter Wallace

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