Problems with Timing Simulation

If you are using the Xilinx ISE tools, then the post-map and post-PAR simulation models will model the "power-on reset" of the FPGA for you automatically (this is completely separate from any user-defined reset signal you might have in your design).

When you generate the simulation models, there is a setting called "Reset On Configuration Pulse width" which defines how long (in nanoseconds) the synchronous elements will wait in their "INIT" states before responding to clock edges. So, it could be that you just need to make your testbench wait for a few hundred nanoseconds before doing anything (or reduce the value of this pulse width when you create the model).

Hope this helps,

-Ben-

Hi Ben,

thank you for your answer.

I am using Lattice ispLEVER 5.0 together with Modelsim.

What do you mean with "that you just need to make your testbench wait for a few hundred nanoseconds before doing anything". ?

After deasserting my reset signal in the testbench, my FSM enters the state s_ini_a. After three clock cycles the first action occurs in the FSM. So how can I wait for a few hundred nanoseconds ? With some kind of enable signal ?

Rgds Andr=E9

Ben Jones schrieb:

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I have added an Enable which gets active after some hundred nanoseconds and the Timing Simulation is OK now :o)

One further question: Are the synchronous elements in the real design immediately ready when leaving Global Reset (Pll is already locked) ? Or is there some "wait" time according to the timing simulation?=20

Thank you for your help.

Rgds Andr=E9

Hi Andre,

Aha. I'm afraid I don't know anything about that! :-)

Well, how does your testebench know how long to wait before deasserting that reset signal? If you're using VHDL then you might have a "wait for" statement somewhere, which you can modify appropriately. If you're using Verilog... well, I don't know anything about that either, I'm afraid.

Of course, as you're using Lattice's tools then there's a very good chance that nothing I've suggested can help you - sorry!

Cheers,

-Ben-

Hi Andre,

Interesting to know that the Lattice simulations models work just like the Xilinx ones in this respect.

time

They are ready immediately. The "wait" time is really just an artefact of the simulation environment. It may be possible when generating your simulation model to pull the "configuration reset" signal out and turn it into a port on the model, so that you can control exactly when it gets de-asserted (relative to other devices in your simulation, for example). However as I mentioned, I've not used the Lattice tools so I'm guessing a bit here!

Glad you got it all working.

-Ben-

Thanks again for your help.

:o)

Andre

Ben Jones schrieb: