Field-Programmable Gate Arrays

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GNU Linker (MicroBlaze) / debugging problem

Is there anyone that knows some "rule of tumb" when creating a linkerscript? the elffile gives me a good idea on how bi...
1 comments posted 21yrs
posted by raybakk
1 comments posted 21yrs posted by raybakk

webcamera access with ML310

I am using ML310 in STANDALONE along with usb based Quickcam expreess(Web camera) for my project on real time image pro...
0 comments posted 21yrs
posted by venkiba81
0 comments posted 21yrs posted by venkiba81

problem with Xilinx OPB to OPB bridge

hello all, I'm building a system with EDK 7.1 on a virtex4 using Xilinx IP and soft processor Microblaze .i'm using 2 O...
0 comments posted 21yrs
posted by bazogec
0 comments posted 21yrs posted by bazogec

some virtexII clock pads are useless??

For test my fpga clock, I input a clock throuth one of the dedicated clock pad, and output it from a general I/O. From...
2 comments posted 21yrs
posted by like609
2 comments posted 21yrs posted by like609

FPGA

HI CAN ANYBODY SUGGEST ME ABOUT READ ADDRESS GENERATOR FORLOGICAL T PHISICAL ADDRESS GENERATO
1 comments posted 21yrs
posted by ravindra28d
1 comments posted 21yrs posted by ravindra28d

struggling with general digital design

Hi everyone! I am new to digital design and need some general advice on it. I have experience with microcontrollers and...
11 comments posted 21yrs
posted by interpasha
11 comments posted 21yrs posted by interpasha

ISE webpack doesnt support Spartan xcs10, solution??

Hiya, Foolishly I developed a board for a spartan 3 xcs10, without finding suitable development enviroment, assuming th...
6 comments posted 21yrs
posted by googlinggoogler
6 comments posted 21yrs posted by googlinggoogler

About post synthesize

hello all, I just want to test my new HDL model it passed the simulation testings. but unfortunately my fpga board is d...
7 comments posted 21yrs
posted by vssumesh_asic
7 comments posted 21yrs posted by vssumesh_asic

Farrow filter VHDL implementation?

Hi Group, Does anyone know how to implement a Farrow FIR filter usng existing FIR cores, or whatever is available? The...
0 comments posted 21yrs
posted by andrewl
0 comments posted 21yrs posted by andrewl

Xilinx ISE WebPACK-7.1i on NetBSD

Here are some tips and two small patches for running ISE WebPACK-7.1i on NetBSD using Linux emulation. Xilinx is now su...
5 comments posted 21yrs
posted by newsposting1
5 comments posted 21yrs posted by newsposting1

Spartan3 Done is not going high

Hello group, I am getting an error from Impact saying that the DONE pin is not going high, Program Terminated, or somet...
3 comments posted 21yrs
posted by bradsmallridge
3 comments posted 21yrs posted by bradsmallridge

VHDL 200x? when?

When should we see VDHL 200x incorporated in our EDA tools?
2 comments posted 21yrs
posted by nospam
2 comments posted 21yrs posted by nospam

2-bit RAM16X In a V2PRo

Does anybody know whether it's possible to configure a slice in a V2PRO as a 2-bit memory element such that you can hav...
0 comments posted 21yrs
posted by jeremy
0 comments posted 21yrs posted by jeremy