Does anybody know whether it's possible to configure a slice in a V2PRO as a 2-bit memory element such that you can have separately addressable read and write ports, but not a write port output?
ie, sort of like a RAM16X1D, but with no SPO port, and two bits wide in two LUTS, instead of 1 bit wide in two LUTs.
It kind of looks like it might be possible, looking at fpga_editor and P48 of the V2P datasheet, but I don't see a clear way to do it - so I was wondering whether or not it could be done?
(On a related note - would MC15 be useful for getting more bits out of a RAM element? The docs indicate its use as an alternate for D in an SRL configuration)
Thanks, Jeremy