Field-Programmable Gate Arrays

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Programmable frequency synthesizer with Xilinx DCM

I'm sorry if this is a trivial question, but I haven't found anything on this topic in the Xilinx site: is it possible...
17 comments posted 21yrs
posted by antonio12358
17 comments posted 21yrs posted by antonio12358

ML401 JTAG configuration problem

While I'm waiting for EDK to be delivered I thought I'd play around with a hardware-only design. I made a trivial LED f...
3 comments posted 21yrs
posted by pfraser
3 comments posted 21yrs posted by pfraser

Porting Actel code

I inherited some code for the Actel fpga. The author said he downloaded the demo toolset (early version) from Actel and...
7 comments posted 21yrs
posted by lbax02.spamguard
7 comments posted 21yrs posted by lbax02.spamguard

Xilinx libraries missing,j83a/c modulator IP core

Hi all, I am using j83a/c modulator IP core of Xilinx in ISE.I have synthesised and implemented the design.I did not an...
0 comments posted 21yrs
posted by monica_dsz
0 comments posted 21yrs posted by monica_dsz

lut problem

hi when i make timing simulation with MODELSIM SE after the synthesis and place and route in XST Tool of Xilinx i never...
0 comments posted 21yrs
posted by lnadjwa
0 comments posted 21yrs posted by lnadjwa

fpga- DDR or DDR2

Hi. I would need to begin a new fpga design intefacing with external SODIMM at a rate of 400 Mbit/sec/pin. I have 2 alt...
4 comments posted 21yrs
posted by nahum_barnea
4 comments posted 21yrs posted by nahum_barnea

AVNET Xilinx Spartan3 board, example problem

Hi all, I am Monica from Germany,I am new to FPGA programming.I have very little experience with Altera cyclone FPGA de...
2 comments posted 21yrs
posted by monica_dsz
2 comments posted 21yrs posted by monica_dsz

Conversion of Schematic to Verilog/VHDL

Does anyone know of a tool that actually converts a schematic entry design to Verilog/VHDL. I know tools like Quartus c...
3 comments posted 21yrs
posted by saurster
3 comments posted 21yrs posted by saurster

circular read address generator

hi i m doing project on image processing.For that i need to store pixe value of any frame in memory. I read from one jo...
3 comments posted 21yrs
posted by ravindra28d
3 comments posted 21yrs posted by ravindra28d

Xilinx Multiple Spartan 3

I have a board with three Spartan3s on it. Right now, under sources in project, I have the project name, then xc3s400-4...
6 comments posted 21yrs
posted by bradsmallridge
6 comments posted 21yrs posted by bradsmallridge

Modifying opb_bram under EDK

I'm trying to create a customized BRAM module (memory redundancy, checkbits) However, the BRAM included in the EDK cann...
3 comments posted 21yrs
posted by Hua.Zheng
3 comments posted 21yrs posted by Hua.Zheng

Spartan3 with WebPack?

Hi: I am reading the FAQ on Spartan3 here: http://www.xilinx.com/products/spartan3/faq105_s3.pdf which says only XC3S50...
3 comments posted 21yrs
posted by crcarleRemoveThis
3 comments posted 21yrs posted by crcarleRemoveThis

Xilinx Best Source for Reset

Up to now, I have been doing much of my work with ModelSim and a BMP file reader and writer. Most of my VHDL designs ha...
16 comments posted 21yrs
posted by bradsmallridge
16 comments posted 21yrs posted by bradsmallridge

Bidirectional Bus problem with ModelSim.

Hello everyone! I am having a problem in ModelSim XE 5.8c with a very simple bidirectional bus. ModelSim outputs a bunc...
3 comments posted 21yrs
posted by interpasha
3 comments posted 21yrs posted by interpasha