Latest threads in Field-Programmable Gate Arrays

ML401 JTAG configuration problem

While I'm waiting for EDK to be delivered I thought I'd play around with a hardware-only design. I made a trivial LED f...

3 21yrs

pfraser

3 21yrs pfraser

Porting Actel code

I inherited some code for the Actel fpga. The author said he downloaded the demo toolset (early version) from Actel and...

7 21yrs

lbax02.spamguard

7 21yrs lbax02.spamguard

Xilinx libraries missing,j83a/c modulator IP core

Hi all, I am using j83a/c modulator IP core of Xilinx in ISE.I have synthesised and implemented the design.I did not an...

0 21yrs

monica_dsz

0 21yrs monica_dsz

How to manage user 'reset' for post-synthesis simulation

Dear I need some comments on managing the 'global reset' in ISE6.3(XST) from experienced one. I am post-placement-and-r...

1 21yrs

pasacco

1 21yrs pasacco

lut problem

hi when i make timing simulation with MODELSIM SE after the synthesis and place and route in XST Tool of Xilinx i never...

0 21yrs

lnadjwa

0 21yrs lnadjwa

fpga- DDR or DDR2

Hi. I would need to begin a new fpga design intefacing with external SODIMM at a rate of 400 Mbit/sec/pin. I have 2 alt...

4 21yrs

nahum_barnea

4 21yrs nahum_barnea

AVNET Xilinx Spartan3 board, example problem

Hi all, I am Monica from Germany,I am new to FPGA programming.I have very little experience with Altera cyclone FPGA de...

2 21yrs

monica_dsz

2 21yrs monica_dsz

Conversion of Schematic to Verilog/VHDL

Does anyone know of a tool that actually converts a schematic entry design to Verilog/VHDL. I know tools like Quartus c...

3 21yrs

saurster

3 21yrs saurster

circular read address generator

hi i m doing project on image processing.For that i need to store pixe value of any frame in memory. I read from one jo...

3 21yrs

ravindra28d

3 21yrs ravindra28d

Xilinx Multiple Spartan 3

I have a board with three Spartan3s on it. Right now, under sources in project, I have the project name, then xc3s400-4...

6 21yrs

bradsmallridge

6 21yrs bradsmallridge

Modifying opb_bram under EDK

I'm trying to create a customized BRAM module (memory redundancy, checkbits) However, the BRAM included in the EDK cann...

3 21yrs

Hua.Zheng

3 21yrs Hua.Zheng

Spartan3 with WebPack?

Hi: I am reading the FAQ on Spartan3 here: http://www.xilinx.com/products/spartan3/faq105_s3.pdf which says only XC3S50...

3 21yrs

crcarleRemoveThis

3 21yrs crcarleRemoveThis

Xilinx Best Source for Reset

Up to now, I have been doing much of my work with ModelSim and a BMP file reader and writer. Most of my VHDL designs ha...

16 21yrs

bradsmallridge

16 21yrs bradsmallridge

Bidirectional Bus problem with ModelSim.

Hello everyone! I am having a problem in ModelSim XE 5.8c with a very simple bidirectional bus. ModelSim outputs a bunc...

3 21yrs

interpasha

3 21yrs interpasha

GNU Linker (MicroBlaze) / debugging problem

Is there anyone that knows some "rule of tumb" when creating a linkerscript? the elffile gives me a good idea on how bi...

1 21yrs

raybakk

1 21yrs raybakk

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