hi
when i make timing simulation with MODELSIM SE after the synthesis and place and route in XST Tool of Xilinx i never met the data in the output i dont know why...please help me
this is my lut description:
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_signed.all;
entity lut_mod is generic(DEEP: integer := 8; WIDTH: integer := 8 ); port( ready : in std_logic; add33: in std_logic_vector(DEEP downto 1); data_lut33: out std_logic_vector(WIDTH downto 1) ); end lut_mod;
architecture archi_lut_mod of lut_mod is subtype WORD is std_logic_vector(WIDTH downto 1); type ROM is array (127 downto -128) of WORD; constant ROM_array : ROM := ( "11111000", "11111000", "11111000", "11111000", "11111000", "11111000", "11111000", "11111000", "11111000", "11111000", "11111000", "11111000", "11111000", "11111000", "11111000", "11111000", "11111001", "11111001", "11111001", "11111001", "11111001", "11111001", "11111001", "11111001", "11111001", "11111001", "11111001", "11111001", "11111001", "11111001", "11111001", "11111001", "11111010", "11111010", "11111010", "11111010", "11111010", "11111010", "11111010", "11111010", "11111010", "11111010", "11111010", "11111010", "11111010", "11111010", "11111010", "11111010", "11111011", "11111011", "11111011", "11111011", "11111011", "11111011", "11111011", "11111011", "11111011", "11111011", "11111011", "11111011", "11111011", "11111011", "11111011", "11111011", "11111100", "11111100", "11111100", "11111100", "11111100", "11111100", "11111100", "11111100", "11111100", "11111100", "11111100", "11111100", "11111100", "11111100", "11111100", "11111100", "11111101", "11111101", "11111101", "11111101", "11111101", "11111101", "11111101", "11111101", "11111101", "11111101", "11111101", "11111101", "11111101", "11111101", "11111101", "11111101", "11111110", "11111110", "11111110", "11111110", "11111110", "11111110", "11111110", "11111110", "11111110", "11111110", "11111110", "11111110", "11111110", "11111110", "11111110", "11111110", "11111111", "11111111", "11111111", "11111111", "11111111", "11111111", "11111111", "11111111", "11111111", "11111111", "11111111", "11111111", "11111111", "11111111", "11111111", "11111111", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000001", "00000001", "00000001", "00000001", "00000001", "00000001", "00000001", "00000001", "00000001", "00000001", "00000001", "00000001", "00000001", "00000001", "00000001", "00000001", "00000010", "00000010", "00000010", "00000010", "00000010", "00000010", "00000010", "00000010", "00000010", "00000010", "00000010", "00000010", "00000010", "00000010", "00000010", "00000010", "00000011", "00000011", "00000011", "00000011", "00000011", "00000011", "00000011", "00000011", "00000011", "00000011", "00000011", "00000011", "00000011", "00000011", "00000011", "00000011", "00000100", "00000100", "00000100", "00000100", "00000100", "00000100", "00000100", "00000100", "00000100", "00000100", "00000100", "00000100", "00000100", "00000100", "00000100", "00000100", "00000101", "00000101", "00000101", "00000101", "00000101", "00000101", "00000101", "00000101", "00000101", "00000101", "00000101", "00000101", "00000101", "00000101", "00000101", "00000101", "00000110", "00000110", "00000110", "00000110", "00000110", "00000110", "00000110", "00000110", "00000110", "00000110", "00000110", "00000110", "00000110", "00000110", "00000110", "00000110", "00000111", "00000111", "00000111", "00000111", "00000111", "00000111", "00000111", "00000111", "00000111", "00000111", "00000111", "00000111", "00000111", "00000111", "00000111", "00000111" ); begin process(add33, ready) begin if ready = '1' then data_lut33