I have a board with three Spartan3s on it. Right now, under sources in project, I have the project name, then xc3s400-4pq208, and under that top1-behavioral(top1.vhd), top2-behavioral(top2.vhd), top3-behavioral(top3.vhd)
and stuf under those like the top1.ucf, etc.
So what happens if one of the Xilinx parts gets upgraded or downgrade in speed or size? Can I assign the xc3s400 spec to each top level design?
Brad
I think when you download programming file (.bit file) that implement with one speed grade to other speed grade fpga, you found an error about id number of device on iMPACT.
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you can not use one project for different (size/family) FPGAs.
the speed grade only matter for timing analyzer, there is no diff in .bit file.
what you need is to setup up commandline scripts to run the synth in batch
Antti
Brad,
As far as I recall, the speed grade affects only timing analysis (xilinx people would correct me if i am wrong).
Downloading a bit file which was synthesized with a different speed grade only is ok.
But if the device is different in size, then you have to resynthesize it, in which case a suitable script would do the job.
Vladislav
Vladislav, what you just wrote is correct. Speed grade does not affect bitstream, only performance. That is true for all Xilinx parts. Peter Alfk
It seems like one should be able to set up one project with multiple parts and be able to assign different packages.
What do the big boys do? I've seen plenty of boards with more than one Xilinx on them.
Brad
Good question
(*) Profound architecturing before coding & methodological approach. (**) Design Automation, scripting (even you have a PC, and not some heavy duty washer like ultrasparc) (***) Choosing a good FPGA design engineer (I'd place this one first on the list)
Vladislav
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