Hello everyone! I am having a problem in ModelSim XE 5.8c with a very simple bidirectional bus. ModelSim outputs a bunch of XXXX's where its supposed to output data. I am using test bench waveforms with Xilinx ISE 6.303i.
Basically there are only 3 signals: the bidir. bus, wr_enable and clk. The idea behind this simple code is: if WR_EN is HIGH -> store bus data into a flip-flop on next clock edge.
else WR_EN is LOW -> output a constant value on the bus (in practice, I want to output something more useful, of course.)
Unfortunately, ModelSim outputs X's (don't cares) for every bit where the data in flip-flop conflicts with the constant. Let's say that 11110000 was stored in the flip-flop when WR_EN was high. And suppose that the constant to put on the bus is 00110000, when WR_EN goes low. When WR_EN actually does go low, ModelSim will output XX110000 instead of 00110000.
I think the problem might be with the way I designed the bus with VHDL. But I can't figure out where the problem is, and the code is VERY simple. Any help on this and maybe references to reading materials on bidirectional/tristate bus implementation in VHDL would be highly appreciated! Thanks, Pavel
Here is the code:
------------------------------ library IEEE; use IEEE.STD_LOGIC_1164.ALL;
------------------------------ ENTITY bidir_bus IS PORT( bidir : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0); WR_en, clk : IN STD_LOGIC); END bidir_bus;
------------------------------ ARCHITECTURE Behavioral OF bidir_bus IS SIGNAL a : STD_LOGIC_VECTOR (7 DOWNTO 0); -- DFF that stores -- value from input. BEGIN PROCESS (WR_en, clk) BEGIN IF( WR_en = '1') THEN bidir