Porting Actel code

I inherited some code for the Actel fpga. The author said he downloaded the demo toolset (early version) from Actel and then reset his PC clock until he was able to finish. My understanding is that the toolchain has changed substantially since he wrote the code.

I need two things: 1 - to be able to read the code/project and determine what it does 2 - to be able to revise/maintain the code.

I would like recommendations as to what toolchain to port this code to. Money is an issue - ROI is quite low.

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Reply to
Baxter
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If the code is a netlist and you don't know what it does, I see little value in maintaining it.

If it is generic RTL code with a testbench, you can make modifications and test them, and port to any fpga you like.

-- Mike Treseler

Reply to
Mike Treseler

I'm new to this kind of programming - I don't know what "netlist" or "RTL" are.

I have a general idea what the code does, I need to find out the nitty-gritty details. As it stands now, I have a binary file I can use to burn chips, but no ability to maintain or extend the code. I'd like to port the design to a slightly different platform -- I'd still be using the same chip, but likely the chip software would have to change slightly.

It's got lots of different files, including some .vhd. I was hoping to find someone with lots of Actel experience.

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Reply to
Baxter

"Baxter" schrieb im Newsbeitrag news: snipped-for-privacy@corp.supernews.com...

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well the .VHD are source files, if all the project is on .VHD files then you have no problems. if part of the design is not, eg is in compiled files or in schematic files not readable by available tools then you have more problems.

Antti

Reply to
Antti Lukats

HI,

based on your other answer I understand you have a .adb file. This is the actel database which should be useable in the newer versions of actel designer software (When having a very old version you might lost your pinout). I hope you didn't mean a .afm file which is only the programming file for the Fpga and will be (nearly [1]) complete useless.

The designer software is available as silver edition for free. This edition is OK for smaller devices. The database contains the netlist which can be exported. But without having any knowledge of rtl and netlist you out yourself as someone who should not even think to modify the netlist to get the desired results.

Start searching .vhd or .v files containing the rtl code (register transfer level). The IMHO better way for you would be starting to learn how to design digital cirquits and rebuild the design from scratch.

bye Thomas

[1] Buying a good support from Actel could help getting some logic out of the bitstream. Actel might have the possibility to get a netlist out of this bitsream.
Reply to
usenet_10

I do have a .adb file - along with a host of others. I've got subdirectories labeled "design_definition", "simulator_build", etc.

I do have a .afm file which I sent off to the Actel distributor when I ordered more chips.

Well, how small? I'm using the eX64 (64 dedicated flip-flops, 3000 system gates)

No "outing" about it - I'm a raw beginner at embedded programming. I'm trying to make sense of what I've got and to determine what I need to do. Among other things, I'm trying to determine if I should continue with this basic design or to switch to an entirely different chip. (a business decision based on technical aspects.)

I've got the book "VDHL Programming by example". I don't know if any of the book's tools would be useable.

As I indicated, the ROI is VERY bad at this point.

Reply to
Baxter

You can't get much smaller than that.

Make that, a raw beginner at digital hardware design.

I've yet to find a CD attached to a book that is worth trouble to unwrap.

Most vendors have "web" editions of their software that you can download for free.

-- Mike Treseler

Reply to
Mike Treseler

Well it is now the Gold edition of Libero/Designer that is free, and that will cope with all devices upto 300,000 gates, and a couple of the larger APA3 devices. So it would be worth downloading and trying to import your design.

If your design is purely VHDL then it is fairly easy just to import the .vhd files and go from there. If there are any ACTGen macros, these are .gen files, then you can also import those and then generate the .vhd files for them, or find out what there are and create your own VHDL files. If there are any ViewDraw schematics in the design, these are .1 files, then it is a little complicated, but can be done.

Reply to
Neill A

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