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Modular design flow

Hello all,

I am currently using xilinx modular design flow to develop a simple design. The top level design has an inout port for communicating data between an external memory and fpga. I have implemented the necessary control logic for this port in one of the modules and port mapped the port of the module to the top level inout port. After having done this when I run (ngdbuild -modular initial top.edd) with all the modules instantiated (black boxes only) I receive the following error "ERROR:NgdBuild:456 - logical net '***' has both active and tristate drivers".

Can anyone suggest what needs to be done in this regard.

Thanks

Reply to
Fpga_Designer
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Did you simulate your design?

The error is clear -- you have two drivers on the same net. A simulation would have shown this.

-a

Reply to
Andy Peters

I figured out what the problem is. Instead of just having inout ports in the module mapped onto the inout ports of the top level entity, I had 3 ports for input,output and control signal from the module and used these signals in the top level design for the inout port.

Reply to
Fpga_Designer

Hello,

I had the same problem when the RAM controller was inside a module. The way I solved the problem was very easy, I converted the bidir port into two and added a port with the control signal of the bidir port. I put the bidir just in the top level, adding also the logic that controls the port something like:

assign data=control?data_i:data_o;

It works perfect with the modular flow.

Javier Castillo

Reply to
Javier Castillo

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