Hi All, I have a state machine which produces control signals (synchronous Reset and Enable) for a synchronous counter. The control signals are generated based on the current state and a 8 bit data input. I am seeing glichtes in both output control signals near the rising clock edges. The 8 bit data input is registered. Is there any way to get rid of the glicthes?
The VHDL code looks something like this
FSM: process(CurrentState,DataIn,Count,NewFrame,...) begin CntrRst
Sudhir, so you have two sets of synchronous signals (hopefully synchronized by the same global clock) and you combine them through combinatorial logic to generate 2 control signals for the counters. Obviously, you will generate glitches on these outputs, as a result of prop delay differences in the combinatorial logic. But these glitches occur a few nanoseconds AFTER the active clock edge, and they are, therefore, irrelevant and cause no harm. The beauty of synchronous logic is that inputs need only be stable during the set-up time BEFORE the clock edge. Peter Alfke, Xilinx Applications (from home)
Peter, thanks for your reply. Sudhir
Peter Alfke wrote:
Have something to add? Share your thoughts — no account required.
Ask the community — no account required