To all,
I'm trying to create a test bench where an array data type of "std_logic_vector" is read within a for loop and then stored to a file. The problem I'm facing is that the array accesses the starting index of 0 twice and doesn't capture the last element of the array as it should. That is the line stated below as: "refmemdata
What is the initialization of refmemdata that is before the first rising edge of clk ?
Rgds Andr=E9
Your code produces a delta between assigning refmemdata and write. Note that signal assignments only update the signal drivers, which update the signal value at the next cycle.
You can insert a wait for 0 ns; statement to let the signal settle:
...
-- Array accessing and file storage stimulus: process() variable data_file_line: line; begin for k in 0 to 4 loop wait until (clk'event) and (clk = '1'); refmemdata
Thanks Hubble. This worked and forgot that the signals have an additional delay compared with variables which can change instantaneously.
Cheers, P> Your code produces a delta between assigning refmemdata and write. Note
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