I am simulating a IPIF + user core using the BFM simulation model and in my test I can succesfully write to the WFIFO (write fifo) and write to the RFIFO (read fifo) but for some reason the data from the read fifo doesn't get dumped to the IP2BUS_DATA (Data Bus) is there any signal that I should assert from the IPIF interface to dumped the data from the RFIFO to the bus?
Thanks, Noel
I'm not sure what you mean, the WFIFO/RFIFO datapaths are separate from the IP2BUS_DATA and BUS2IP_DATA signals. The IPIF generated by the IP Import Wizard automatically connects things up internally to get data to/from RFIFO/WFIFO to the bus.
Are you planning on using the vacancy/occupancy counters for the FIFOs? I see them working in simulation but running on the hardware, reading each from the processor always returns zero. Empty/Full and the FIFO operations themselves are working in both hardware and software.
Paul
el_boricua wrote:
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