Well it is fully asynchronous design - sort of concept-proof, more in demonstration purposes. I know FPGA is not the proper platform for it at all, however everything is working fine, apart that problem.
So can anyone help with the problem when the synthesiser optimize the design by throwing buffer elements away?
Hi guys.
Implementing asynchronous delays in my design via a chain of buffer elements (I know it's a bad practise, but I need few ns delays) I faced the problem with removing them from the design, as Xilinx synthesiser removes these elements from the design, although the OPTIMIZE option is off.
So I'd like to ask if anyone can tell me where I missed something, and also if someone already implemented small delays via internal FPGA units (not RC chains)which elements may provide the biggest delay (in order to save space).
Thanks a lot.
Why do you need an async delay?
-a
Look up the "keep" and "save" attributes.
Can't remember which does what (been too long since I played games like you are doing), but if you want the logic there that you put in, and do not want it optimized out.
Austin
Alex wrote:
Thanks it helped! Maybe if you have some experience you can suggest how maximise delay, using minimum hardware. I can gues that to use most of the slice hardware something like a chain LUT->mux->FF, but is it possible to implement two of chains within one slice (Spartan3) via manual placing; or maybe there are some other ways? The design is internal so I can't play with IOB's and external logic.
Thanks
Have something to add? Share your thoughts — no account required.
Ask the community — no account required