Field-Programmable Gate Arrays

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Monitor the internal signal of EDF using chipscope

Hello guys, I am integrating a IP which is available has EDF netlist format. I am facing some problem in this IP. So in...
0 comments posted 21yrs
posted by stud_lang_jap
0 comments posted 21yrs posted by stud_lang_jap

Xilinx PC4 Download Cable

I am having trouble to program the XCF08P on an Avnet V4LX-EVL-25 evaluation board. The Platform Flash is a ES (Engenee...
1 comments posted 21yrs
posted by email
1 comments posted 21yrs posted by email

Altera nios-debug via JTAG

Hi, I have been trying to debugg a simple "hello world" program running in an Altera Cyclone device with Nios 32 (inclu...
0 comments posted 21yrs
posted by evan1979
0 comments posted 21yrs posted by evan1979

digilent spartan 3 kit example project

does any one know where to find some example projects for spartan 3 starter board for digilent. CMOS
3 comments posted 21yrs
posted by manusha
3 comments posted 21yrs posted by manusha

Bootloading with flash-config devices

Hi everyone, Sorry if this topic has come up before - I have read numerous threads on this newsgroups regarding this to...
1 comments posted 21yrs
posted by jai.dhar
1 comments posted 21yrs posted by jai.dhar

Maybe a very cool FPGA a throw away idea for Xilinx

Why doesn't Xininx include a simple programmable bus manager like Mr. Moore's 25X for fabrication efficiency or applica...
0 comments posted 21yrs
posted by cpu16x1832
0 comments posted 21yrs posted by cpu16x1832

Question about program and memory location

Hallo, I have made a small microcontroller based on microblaze. I have copied into lmb bram a bootloader which copies m...
0 comments posted 21yrs
posted by marcotoschi
0 comments posted 21yrs posted by marcotoschi

CPLD Jitter

The dividers and the phase detector of my experimental frequency synthesizer are implemented in a 15ns Altera MAX7000S...
20 comments posted 21yrs
posted by andrew
20 comments posted 21yrs posted by andrew

mails from Aman Mediratta

I was just wondering if also other peoples in this group get private mails from Aman Mediratta, asking for technical su...
9 comments posted 21yrs
posted by aon.912710880
9 comments posted 21yrs posted by aon.912710880

How to reduce software size?

Hallo, I need to run a small software into bram. The trouble is with function: XUtil_MemoryTest32 It increases software...
0 comments posted 21yrs
posted by marcotoschi
0 comments posted 21yrs posted by marcotoschi

Altera Avalon Master/Slave User Defined Logic?

To all, Is it possible to create a user defined logic that is both a master and a slave peripheral? What I want to impl...
0 comments posted 21yrs
posted by pinod01
0 comments posted 21yrs posted by pinod01

Feedback signal cancellation algorithm

Hi, I am going to do a research project which needs to cancel feedback data signal of an amplifier. The data signal fre...
0 comments posted 21yrs
posted by eehobbyist
0 comments posted 21yrs posted by eehobbyist

Clock skew in FPGA Xilinx?

Dear all, In ASIC design, clock skew can be solved by using Clock tree generation. How does FPGA solve it?Use the clock...
2 comments posted 21yrs
posted by yijun_lily
2 comments posted 21yrs posted by yijun_lily