Latest threads in Field-Programmable Gate Arrays

fast universal compression scheme and its implementation in VHDL

Hi folks, my name is Jens and I am student of the Technical University Berlin. Through my course of study in microelect...

3 21yrs

quinn_the_esquimo

3 21yrs quinn_the_esquimo

Xilinx PC4 Download Cable

I am having trouble to program the XCF08P on an Avnet V4LX-EVL-25 evaluation board. The Platform Flash is a ES (Engenee...

1 21yrs

email

1 21yrs email

Altera nios-debug via JTAG

Hi, I have been trying to debugg a simple "hello world" program running in an Altera Cyclone device with Nios 32 (inclu...

0 21yrs

evan1979

0 21yrs evan1979

digilent spartan 3 kit example project

does any one know where to find some example projects for spartan 3 starter board for digilent. CMOS

3 21yrs

manusha

3 21yrs manusha

Bootloading with flash-config devices

Hi everyone, Sorry if this topic has come up before - I have read numerous threads on this newsgroups regarding this to...

1 21yrs

jai.dhar

1 21yrs jai.dhar

Maybe a very cool FPGA a throw away idea for Xilinx

Why doesn't Xininx include a simple programmable bus manager like Mr. Moore's 25X for fabrication efficiency or applica...

0 21yrs

cpu16x1832

0 21yrs cpu16x1832

Question about program and memory location

Hallo, I have made a small microcontroller based on microblaze. I have copied into lmb bram a bootloader which copies m...

0 21yrs

marcotoschi

0 21yrs marcotoschi

CPLD Jitter

The dividers and the phase detector of my experimental frequency synthesizer are implemented in a 15ns Altera MAX7000S...

20 21yrs

andrew

20 21yrs andrew

mails from Aman Mediratta

I was just wondering if also other peoples in this group get private mails from Aman Mediratta, asking for technical su...

9 21yrs

aon.912710880

9 21yrs aon.912710880

How to reduce software size?

Hallo, I need to run a small software into bram. The trouble is with function: XUtil_MemoryTest32 It increases software...

0 21yrs

marcotoschi

0 21yrs marcotoschi

Altera Avalon Master/Slave User Defined Logic?

To all, Is it possible to create a user defined logic that is both a master and a slave peripheral? What I want to impl...

0 21yrs

pinod01

0 21yrs pinod01

Feedback signal cancellation algorithm

Hi, I am going to do a research project which needs to cancel feedback data signal of an amplifier. The data signal fre...

0 21yrs

eehobbyist

0 21yrs eehobbyist

connecting block ram to datapath using bidirectional lines

Hi ,I've been working on this for three days and I got lost in the se of XST warnings and errors .... I'm really lost.....

0 21yrs

mib2500

0 21yrs mib2500

Clock skew in FPGA Xilinx?

Dear all, In ASIC design, clock skew can be solved by using Clock tree generation. How does FPGA solve it?Use the clock...

2 21yrs

yijun_lily

2 21yrs yijun_lily

Should I use DCM for every FPGA design?

I am a newbie in Xilinx FPGA and am trying to prototype my own architecture. I tried the tutorial about stopwatch. Ever...

3 21yrs

yijun_lily

3 21yrs yijun_lily

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