Hello guys, I am integrating a IP which is available has EDF netlist format. I am facing some problem in this IP. So in order to debug the IP i have to monitor certain internal signal of the IP. I am synthesizing my top module which contain IP has black box and other supporting logic. I then insert the chipscope module to this netlist (top module netlist) but in the chipscope I am not able to see the internal IP signal, this may be due to IP core being a black box. Can i preserve the signal which i monitor through chipscope. I don't want to change the EDF file as it is tedious job. I am using synplify for synthesis.
Waiting for your reply Thanks and regards Williams