Just curious if anyone else has come across this:
I have a design using an asynchronous fifo. It builds without any problems in ISE 6.3. When I upgraded to ISE 7.1, I get the following error when I build the bitstream:
ERROR:PhysDesignRules:993 - Dangling pins on block :. Must have a VCC signal on the input control path.
I originally generated the fifo using the 6.3 core generator. I recreated it with the 7.1 core generator (including the IP updates), and I get the same problem. If I choose to skip the DRC, the design works fine. However, I would prefer not to skip it.
If I open the FPGA Editor, and run the DRC, and get the same PhysDesignRules:993, but it's a warning, not an ERROR