Dear all, I'd like to understand why my design, which occupies 2500 Slice according to Precision RTL, increases to 3900 Slices after running Xilinx ISE Translate and Map. The synthesized design is passed in EDIF format from Precision to ISE. Any explanation about that ?
Thanks in advance.
Because of packing factor, I can put bet that "precision RTL" is taking total number of FFs and LUTs and is dividing with 4 (assuming V2, V2P, V4, S3) and is getting the mumber of slices. Map is responsible of packing this and very likely will not be able to pack 100% (every single slice should have all the luts and FFs used) try to see how many FF and LUTs is "precision RTL" reporting and compare with the number of FF and LUTs reported by map.
Aurash
snipped-for-privacy@laben.it wrote:
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