I've just started to use the XUP Virtex-II Pro, but I hit a problem I can't seem to solve or circumvent:
I'm using EDK 6.3, and when I generate a system containing DDR in XPS, I get the following errors during compile time:
Constructing platform-level signal connectivity ... ERROR:MDT - pgassign1 - assign index is out of VEC range, [0:1] ERROR:MDT - pgassign1 - assign index is out of VEC range, [0:1] ERROR:MDT - pgassign2 - assign index is out of VEC range, [0:1] Completion time: 13.00 seconds ERROR:MDT - platgen failed with errors! make: *** [implementation/system.bmm] Error 2 Done.
It seems the system has a problem creating the top-level connections. I have no idea how to "fix" this. I haven't changed any settings after generation.
As far as I know, the PGassign signals are "temporaty" signals created by XPS when merging nets (for example, to merge the clock inputs of the DDR memory with padding '0' signals). But I'm not sure about this.
Anyone know what to do?
Thank you in advance!