Modelsim XE and multi-file Verilog projects

Hi, I'm currently designing a disc drive controller to interface with a

6502-based system. To ease the design a little, I've split it up into a few different modules which are all used by a module called "fdd_top". Now, if I simulate any of the child modules that fdd_top uses, I can simulate the module perfectly with Modelsim XE. That, of course, is what is supposed to happen. The problems start when I try and simulate fdd_top: nothing works! All the outputs are shown as "X". Is there some setting in Modelsim or ISE7.1 that I need to tweak to get MXE to simulate the children as well as the fdd_top module?

Sorry if this question sounds a bit silly, but I only started learning howw to use CPLDs last week (using XC9500XL CPLDs, but I want some Coolrunner XPLA3s to play with - shame no-one seems to want to sell me any - same goes for the >72 macrocell XC9500XLs). I've worked out most of the basics of Verilog from studying other people's code (and reading some of the guides on fpga4fun) but still need to work out how the "

Reply to
Philip Pemberton
Loading thread data ...

I am facing the same problem.....looking forward to advice from the experienced members in the group !

thanks, TD

Philip Pembert> Hi,

Reply to
TD

Your problem may be that the flipflops aren't initialized. If you're building something that depends on the previous state, such as a counter, it will generate XXX unless you have a way to force some known initial state. This could be done using a reset in your code, or by using an initial statement to set up the initial state.

Regarding I'm currently designing a disc drive controller to interface with a

Reply to
Marko

Let me be more specific than Marko was.

Reply to
gallen

For more info on blocking vs non-blocking assignments, look at

formatting link

In general, the previous advice is good, ie if you use posedge or negedge, you probably should use

Reply to
johnp

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.