Hi, I'm currently designing a disc drive controller to interface with a
6502-based system. To ease the design a little, I've split it up into a few different modules which are all used by a module called "fdd_top". Now, if I simulate any of the child modules that fdd_top uses, I can simulate the module perfectly with Modelsim XE. That, of course, is what is supposed to happen. The problems start when I try and simulate fdd_top: nothing works! All the outputs are shown as "X". Is there some setting in Modelsim or ISE7.1 that I need to tweak to get MXE to simulate the children as well as the fdd_top module?Sorry if this question sounds a bit silly, but I only started learning howw to use CPLDs last week (using XC9500XL CPLDs, but I want some Coolrunner XPLA3s to play with - shame no-one seems to want to sell me any - same goes for the >72 macrocell XC9500XLs). I've worked out most of the basics of Verilog from studying other people's code (and reading some of the guides on fpga4fun) but still need to work out how the "