Field-Programmable Gate Arrays

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Mentor FPGA Advantage, a simple question

I'm using Mentor Fpga Advantage 7.0 and really, I read the docs but I can't figure the difference between "through bloc...
2 comments posted 21yrs
posted by fake
2 comments posted 21yrs posted by fake

FS: Lot of 60 XCV1000 FPGAs

Hi. I have a sealed, un-opened, 60-pack of XCV1000-4BG560C FPGAs for sale. They are in the original Xilinx packaging, s...
4 comments posted 21yrs
posted by r_fpga_dev
4 comments posted 21yrs posted by r_fpga_dev

New PCI Express Group

Folks, A new group specifically for PCI Express has been started at: http://groups.google.com/group/PCI-Express This gr...
0 comments posted 21yrs
posted by msmith3
0 comments posted 21yrs posted by msmith3

Spartan 3 Serdes

Currently I am transfering 9 bits of data from one Spartan 3 to another using 9 LVCMOS25 lines. A 30 MHz clock supplies...
7 comments posted 21yrs
posted by bradsmallridge
7 comments posted 21yrs posted by bradsmallridge

Spartan-3 LVDS driving TFT LCD panel..?

Does anyone know how feasible it is to drive a TFT panel LVDS interface (sometimes called Panel-link I think) direct fr...
6 comments posted 21yrs
posted by mike
6 comments posted 21yrs posted by mike

Hello A newbie to FPGA

Currently doing a project in school relating to FPGA. Will try t explore more here and hope to interact with the members...
1 comments posted 21yrs
posted by davetolove
1 comments posted 21yrs posted by davetolove

ZIF press-fit socket for QFP FPGA packages

Hi all I want to use FPGAs in 100 or 144 pin quad flat-pack (QFP) packaging. I really want to be able to socket these s...
1 comments posted 21yrs
posted by vadimv
1 comments posted 21yrs posted by vadimv

Problems on Xilinx FIR Core

I wanna implement a digital filter with my XC2S200E, but I'm not very know about DSP theory. I find Xilinx provide MAC...
0 comments posted 21yrs
posted by sutongqi
0 comments posted 21yrs posted by sutongqi

chipscope commands?

Hello, I am looking for an Chipscope-command to put in an Batch-file. I want to read out Data´s over night with CS and...
1 comments posted 21yrs
posted by Nightstorm
1 comments posted 21yrs posted by Nightstorm

Hi-Z input

Hallo, have connected an external signal to my spartan 3. When the external peripheral goes into power down mode, the s...
9 comments posted 21yrs
posted by marcotoschi
9 comments posted 21yrs posted by marcotoschi

modular design: can one use long lines

Can one use horizontal long lines to pass signals between two modules over a third one in modular-based flow? what about...
0 comments posted 21yrs
posted by john.wo.71
0 comments posted 21yrs posted by john.wo.71

Low Power RTL Design

Hi All.. I'm now about to carry a low-power design, I've searched the net for low power design resources, but most of t...
4 comments posted 21yrs
posted by mhosni80
4 comments posted 21yrs posted by mhosni80

Virtex4 : Downloading error

I created microblaze design using bases system builder for virtex 4 lx25 lc board using Xilinx EDK 7.1i sp2. After down...
1 comments posted 21yrs
posted by cybershakith
1 comments posted 21yrs posted by cybershakith

Implementing PLL in Cyclone - Schematic entry

Hi folks, I'm new to the Quartus software. Can someone tell me how to implement a PLL in the schematic entry mode using...
1 comments posted 21yrs
posted by LeonardGabrielson
1 comments posted 21yrs posted by LeonardGabrielson