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current!

We have a 3.3 volt uP that's programming two Spartan 3 FPGAs in slave serial mode. A CPU port pin drives a 180 ohm series resistor to the line that CCLKs both FPGAs, with a 330 ohm resistor to ground at the last one, making a nice voltage divider for the 2.5 volt dedicated config logic. It works fine and both chips configure nicely.

But if we probe the resistor junction before we configure either chip, which is both chip's CCLK pins, we get about +0.6 volts with the CPU port pin at ground. Clearly one or both of the CCLK pins is sourcing current... about 5 mA total!

All FPGA ground pins seem to be properly grounded. Anybody have ideas?

John

Reply to
John Larkin
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The current through pullup resistors for dedicated pins at Vcco of 3.3V is up to 2.35 mA per device according to the Spartan-3 FPGA Family: DC and Switching Characteristics (v1.6) datasheet, Table 6.

These signals are probably only pulled high when the HSWAP_EN pin indicates pullups should be used in the unconfigured state.

The Spartan-3 is - as far as I know - the only family with these strong pullups; the Spartan-3E devices are back to the weaker pullups typical of other Xilinx devices.

Reply to
John_H

OK, thanks a lot. I never would have suspected a dedicated CMOS clock input of having/needing a pullup! At least nothing's broke.

John

Reply to
John Larkin

It depends on the mode as to whether the CCLK is an input or an output, hence this dedicated pin is not a dedicated input.

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Reply to
John_H

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