"Perform Timing-Driven Packing and Placement" error?


I am using the Xilinx ISE 7.1 with ModelSim 6.0a and I have a problem when I use the "Perform Timing-Driven Packing and Placement" option for the mapping process.

When I turn that option off my design works perfectly: during all simulations I get the outputs that I expect. But when I turn the option on the Post-Map and Post-PAR simulations give different outputs. It is as if the circuit suddenly performs a different computation.

My circuit was designed for the Virtex-4 and only uses flip-flops and the DSP48 blocks of the FPGA. All the components are connected to the same clock and I am not running the circuit anywhere near its maximum frequency. So I find it odd that an option which should only influence the timing of the circuit (and leave the functional correctness intact) causes this problem.

My guess would be that this is some kind of bug in the mapping process. However, I am quite new to FPGA programming and therefore it is more likely that I made some mistake.

In any case, any help to give me some insight in this problem would be appreciated.

Thank you,


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Hi Martin,

No, it is most likely not your error. There are known problems with the DSP48 register-balancing feature of the mapper. Set the variable XIL_MAP_NO_DSP_AUTOREG in your environment and your problem will most likely disappear.

You may find that upgrading to the latest service pack will also fix it, but unfortunately this is far from certain I'm afraid. If you can submit your design (or part of it) to Xilinx for analysis, that would be really great. The Map team are keen to get to the bottom of these problems.

Sorry for the inconvenience...



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Ben Jones

ISE 7.1 has been a nightmare of bugs. You might try using ISE6.3sp3 instead.

--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
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Ray Andraka

Thank you.

The service pack didn't help, but setting the environment variable did.

So now I can get a working design by:

1) disabling "Perform Timing-Driven Packing and Placement" and leaving XIL_MAP_NO_DSP_AUTOREG unset. 2) enabling "Perform Timing-Driven Packing and Placement" and setting XIL_MAP_NO_DSP_AUTOREG.

However, option 1 results in the circuit with the highest maximum clock frequency so option 2 does not seem to be the better solution. So, for now, I will stick to my original solution (option 1).

I am willing to submit part of the design to Xilinx for analysis. The performance difference between option 1 and 2 is not very significant in that part, but it is visible.

So, where can I submit it?

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Thank you,

I will try to find an older version of the ISE Webpack on the Xilinx website. (No luck so far, if anybody has a link I would like to hear about it.)

[Barely resisting the urge to rant about bad quality software]
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