Hello,
I am using the Xilinx ISE 7.1 with ModelSim 6.0a and I have a problem when I use the "Perform Timing-Driven Packing and Placement" option for the mapping process.
When I turn that option off my design works perfectly: during all simulations I get the outputs that I expect. But when I turn the option on the Post-Map and Post-PAR simulations give different outputs. It is as if the circuit suddenly performs a different computation.
My circuit was designed for the Virtex-4 and only uses flip-flops and the DSP48 blocks of the FPGA. All the components are connected to the same clock and I am not running the circuit anywhere near its maximum frequency. So I find it odd that an option which should only influence the timing of the circuit (and leave the functional correctness intact) causes this problem.
My guess would be that this is some kind of bug in the mapping process. However, I am quite new to FPGA programming and therefore it is more likely that I made some mistake.
In any case, any help to give me some insight in this problem would be appreciated.
Thank you,
Martin