Latest threads in Field-Programmable Gate Arrays

Strange warning "WARNING:MapLib:701 - Signal P_GPIO_3 connected to top level port P_GPIO_3 has been removed."

Hello All, I am facing a very bugging problem while using XILINX ISE 7.1i with SP4 installed. Some of my top level port...

2 21yrs

vijayandra.poojari

2 21yrs vijayandra.poojari

Area Estimation Issues

Hello all, I'd like to ask the following. My design has 3 different generic inputs according to which it multiply insta...

0 21yrs

skatoulas

0 21yrs skatoulas

PPC405 32 bit aligned accesses

Hello everybody, Hopefully someone can give me a hand with a PPC405 issue... How do you configure the PPC so that it on...

15 21yrs

delete

15 21yrs delete

False values in Quartus In-System Memory Editor

Hi. I have a problem with the In-System Memory Editor in Quarts II 4.1. I can read the memory contents and get the corr...

6 21yrs

fpga

6 21yrs fpga

Nand Flash Emulator

Hi, Ive been trying to find some Nand Flash Emulator for my nand Flash driver to be tested....i cud'nt find one... Is an...

0 21yrs

osIndgy

0 21yrs osIndgy

Fastest input IOB on a Spartan-3?

Hi everyone, I'd like to know which input pin/IOB of the Spartan-3 would be able to toggle (divide by 2) the highest fr...

8 21yrs

p.boven

8 21yrs p.boven

Defining Environment variables inside EDK

Hi, I need to define some environment variable to change the behavior of the synthesis tool in order for my design to c...

2 21yrs

com.246tNt

2 21yrs com.246tNt

Reprogramming one MAXII EPM1270 vs security bit set

Hi group, I would like to share an impression I have. Trying to erase and/or reprogram one Altera MAXII EPM1270 device...

2 21yrs

abeaujean

2 21yrs abeaujean

Reading internal signals through a testbench.

Hi all, Through a testbench (Verilog or VHDL), how do I read the values of signals of a sub module through a top module...

4 21yrs

Puneetsingh81

4 21yrs Puneetsingh81

coe file of Xilinx MAC FIR core??

I know that "coewrite" in matlab could give out the coe file for Xilinx DA FIR core. but it seems that the same method...

1 21yrs

sutongqi

1 21yrs sutongqi

Problem with interfacingT-VPACK with ALTERA QUIP5.0

Hi All, I am having problem when interfacing T-VPACK (http://www.eecg.toronto.edu/~vaughn/vpr/vpr.html) with QUIP5.0. I...

4 21yrs

narayan.subramanian

4 21yrs narayan.subramanian

Quartus web edition simulation with off-chip logic?

Hi, list, I am using Quartus II 4.2 and 5.0 (on two different machines) web-editions for MAX II design. The chip is don...

0 21yrs

VAX9000

0 21yrs VAX9000

Partial Reconfiguration : New Forum

My name is Michael and I am entering this technique of partial re-configuration. I am starting new Group of PR users. A...

1 21yrs

michael

1 21yrs michael

Logic??

What logic is needed for the 4 bit add pipe to write the VHDL program????

5 21yrs

kumarssss

5 21yrs kumarssss

IC design contract

if you or your friend have PCI-Express and 10G ethernet MAC design experience successful,plz email me. there is a PCI-Ex...

0 21yrs

cell_rx

0 21yrs cell_rx

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