Field-Programmable Gate Arrays

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Area Estimation Issues

Hello all, I'd like to ask the following. My design has 3 different generic inputs according to which it multiply insta...
0 comments posted 20yrs
posted by skatoulas
0 comments posted 20yrs posted by skatoulas

PPC405 32 bit aligned accesses

Hello everybody, Hopefully someone can give me a hand with a PPC405 issue... How do you configure the PPC so that it on...
15 comments posted 20yrs
posted by delete
15 comments posted 20yrs posted by delete

False values in Quartus In-System Memory Editor

Hi. I have a problem with the In-System Memory Editor in Quarts II 4.1. I can read the memory contents and get the corr...
6 comments posted 20yrs
posted by fpga
6 comments posted 20yrs posted by fpga

Nand Flash Emulator

Hi, Ive been trying to find some Nand Flash Emulator for my nand Flash driver to be tested....i cud'nt find one... Is an...
0 comments posted 20yrs
posted by osIndgy
0 comments posted 20yrs posted by osIndgy

Fastest input IOB on a Spartan-3?

Hi everyone, I'd like to know which input pin/IOB of the Spartan-3 would be able to toggle (divide by 2) the highest fr...
8 comments posted 20yrs
posted by p.boven
8 comments posted 20yrs posted by p.boven

Defining Environment variables inside EDK

Hi, I need to define some environment variable to change the behavior of the synthesis tool in order for my design to c...
2 comments posted 20yrs
posted by com.246tNt
2 comments posted 20yrs posted by com.246tNt

Reading internal signals through a testbench.

Hi all, Through a testbench (Verilog or VHDL), how do I read the values of signals of a sub module through a top module...
4 comments posted 20yrs
posted by Puneetsingh81
4 comments posted 20yrs posted by Puneetsingh81

coe file of Xilinx MAC FIR core??

I know that "coewrite" in matlab could give out the coe file for Xilinx DA FIR core. but it seems that the same method...
1 comments posted 20yrs
posted by sutongqi
1 comments posted 20yrs posted by sutongqi

Problem with interfacingT-VPACK with ALTERA QUIP5.0

Hi All, I am having problem when interfacing T-VPACK (http://www.eecg.toronto.edu/~vaughn/vpr/vpr.html) with QUIP5.0. I...
4 comments posted 20yrs
posted by narayan.subramanian
4 comments posted 20yrs posted by narayan.subramanian

Partial Reconfiguration : New Forum

My name is Michael and I am entering this technique of partial re-configuration. I am starting new Group of PR users. A...
1 comments posted 20yrs
posted by michael
1 comments posted 20yrs posted by michael

Logic??

What logic is needed for the 4 bit add pipe to write the VHDL program????
5 comments posted 20yrs
posted by kumarssss
5 comments posted 20yrs posted by kumarssss

IC design contract

if you or your friend have PCI-Express and 10G ethernet MAC design experience successful,plz email me. there is a PCI-Ex...
0 comments posted 20yrs
posted by cell_rx
0 comments posted 20yrs posted by cell_rx

Long Multiplication

Hi : I am just completing a control system implemented on a Cyclone using Quartus, entirely in schematic with loads of...
2 comments posted 20yrs
posted by xxx
2 comments posted 20yrs posted by xxx