Strange warning "WARNING:MapLib:701 - Signal P_GPIO_3 connected to top level port P_GPIO_3 has been removed."

Hello All,

I am facing a very bugging problem while using XILINX ISE 7.1i with SP4 installed.

Some of my top level ports has been removed by the MAP utility of ISE.The synthesis is successfully completing without any errors or warnings. The post synthesis simulation model shows all the ports and its related logic.

However after the MAP process has been completed, its throws up a warning saying that some top level ports has been removed.(WARNING:MapLib:701 - Signal P_GPIO_3 connected to top level port P_GPIO_3 has been removed.")

Please respond if any one has encountered such problems before.

Regards, VSP

Reply to
VSP
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Without more details, it is difficult to see what is really happening, but I would check:

a) This signal is routed to a PAD. If it is not, and it is an unconnected output, it will be removed

b) It is connected to on output pin, but no PAD is automatically created, set option Synthesis/Xilinx Specific Options/Add I/O Buffers to true

If it is not so, please send more spsecific info.

Reply to
Zara

In the directory where ISE puts all the report files, look for a file named .mrp. This is the mapper report file. Search through the file for the name of the pin that was removed. Search backwards through the file for the first line before this that is not indented. This should be the source of the reason why the pin is being removed.

Reply to
Duane Clark

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