Hello All,
I am facing a very bugging problem while using XILINX ISE 7.1i with SP4 installed.
Some of my top level ports has been removed by the MAP utility of ISE.The synthesis is successfully completing without any errors or warnings. The post synthesis simulation model shows all the ports and its related logic.
However after the MAP process has been completed, its throws up a warning saying that some top level ports has been removed.(WARNING:MapLib:701 - Signal P_GPIO_3 connected to top level port P_GPIO_3 has been removed.")
Please respond if any one has encountered such problems before.
Regards, VSP